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M-8870 の電気的特性と機能

M-8870のメーカーはClareです、この部品の機能は「DTMF Receiver」です。


製品の詳細 ( Datasheet PDF )

部品番号 M-8870
部品説明 DTMF Receiver
メーカ Clare
ロゴ Clare ロゴ 




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M-8870 Datasheet, M-8870 PDF,ピン配置, 機能
M-8870 DTMF Receiver
Low power consumption
· Adjustable acquisition and release times
· Central office quality and performance
· Power-down and inhibit modes (-02 only)
· Inexpensive 3.58 MHz time base
· Single 5 volt power supply
· Dial tone suppression
·· Applications include: telephone switch equipment,
remote data entry, paging systems, personal
computers, credit card systems
The M-8870 is a full DTMF Receiver that integrates both
bandsplit filter and decoder functions into a single 18-pin DIP
or SOIC package. Manufactured using CMOS process tech-
nology, the M-8870 offers low power consumption (35 mW max)
and precise data handling. Its filter section uses switched ca-
pacitor technology for both the high and low group filters and
for dial tone rejection. Its decoder uses digital counting tech-
niques to detect and decode all 16 DTMF tone pairs into a 4-
bit code. External component count is minimized by provision
of an on-chip differential input amplifier, clock generator, and
latched tri-state interface bus. Minimal external components
required include a low-cost 3.579545 MHz color burst crystal,
a timing resistor, and a timing capacitor.
Figure 1 Pin Connections
The M-8870-02 provides a “power-down” option which, when
enabled, drops consumption to less than 0.5 mW.The M-8870-
02 can also inhibit the decoding of fourth column digits (see
Table 5).
40-406-00011, Rev. F
Figure 2 Block Diagram
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M-8870 pdf, ピン配列
M-8870
Table 1 Pin Functions
Pin Name
Description
1 IN+ Non-inverting input Connections to the front-end differential amplifier.
2 IN- Inverting input
3 GS Gain select. Gives access to output of front-end amplifier for connection of feedback resistor.
4 VREF Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail.
5 INH* Inhibits detection of tones representing keys A, B, C, and D.
6 PD* Power down. Logic high powers down the device and inhibits the oscillator. Internal pulldown.
7 OSC1 Clock input
3.579545 MHz crystal connected between these pins completes the internal oscillator.
8 OSC2 Clock output
9 VSS Negative power supply (normally connected to 0 V).
10 OE Tri-statable output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup.
11 - 14 Q1, Q2, Tri-statable data outputs. When enabled by OE, provides the code corresponding to the last valid tone pair received (see
Q3, Q4 Table 5).
15 StD Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is up-
dated. Returns to logic low when the voltage on St/GT falls below VTSt.
16 ESt Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (sig-
nal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
17 St/GT Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register
the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair.
The GT output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St.
(See Figure 7).
18 VDD Positive power supply. (Normally connected to +5V.)
* -02 only. Connect to VSS for -01 version
Guard time adjustment also allows the designer to tailor system
parameters such as talkoff and noise immunity. Increasing tREC
improves talkoff performance, since it reduces the probability
that tones simulated by speech will maintain signal condition
long enough to be registered. On the other hand, a relatively
short tREC with a long tDO would be appropriate for extremely
noisy environments where fast acquisition time and immunity to
dropouts would be required. Design information for guard time
adjustment is shown in Figure 5.
Power-down and Inhibit Mode ( -02 only)
A logic high applied to pin 6 (PD) will place the device into
standby mode to minimize power consumption. It stops the os-
cillator and the functioning of the filters. On the M-8870-01 mod-
els, this pin is tied to ground (logic low).
Inhibit mode is enabled by a logic high input to pin 5 (INH). It in-
hibits the detection of 1633 Hz. The output code will remain the
same as the previous detected code (see Table 1). On the
M-8870-01 models, this pin is tied to ground (logic low).
Input Configuration
The input arrangement of the M-8870 provides a differential in-
put operational amplifier as well as a bias source (VREF) to bias
the inputs at mid-rail. Provision is made for connection of a feed-
back resistor to the op-amp output (GS) for gain adjustment.
In a single-ended configuration, the input pins are connected as
shown in Figure 4 with the op-amp connected for unity gain and
VREF biasing the input at 1/2VDD. Figure 6 shows the differential
configuration, which permits gain adjustment with the feedback
resistor R5.
DTMF Clock Circuit
The internal clock circuit is completed with the addition of a stan-
dard 3.579545 MHz television color burst crystal. The crystal
can be connected to a single M-8870 as shown in Figure 4, or to
a series of M-8870s. As illustrated in Figure 7, a single crystal
can be used to connect a series of M-8870s by coupling the os-
cillator output of each M-8870 through a 30 pF capacitor to the
oscillator input of the next M-8870.
Figure 5 Guard Time Adjustment
40-406-00011, Rev. F
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3Pages


M-8870 電子部品, 半導体
M-8870
Table 6 AC Specifications
Parameter
Symbol Min Typ* Max Units
Notes
Valid input signal levels (each tone of com-
posite signal)
-29
27.5
+1 dBm
869 mVRMS
1,2,3,4,5,8
Positive twist accept
Negative twist accept
10 dB
10 dB
2,3,4,8
Frequency deviation accept limit
± 1.5% + 2 Hz Nom.
2,3,5,8,10
Frequency deviation reject limit
Third tone tolerance
±3.5%
-25
-16
Nom.
dB
2,3,5
2,3,4,5,8,9,13,14
Noise tolerance
-12 dB 2,3,4,5,6,8,9
Dial tone tolerance
+18 +22
dB 2,3,4,5,7,8,9
Tone present detection time
Tone absent detection time
tDP 5 8
tDA 0.5 3
14 ms
8.5 ms
See Figure 8
Minimum tone duration accept
tREC
40 ms
Maximum tone duration reject
tREC
20
ms User adjustable (see Figures 3
Minimum interdigit pause accept
tID
40 ms
and 5)
Maximum interdigit pause reject
tDO 20
ms
Propagation delay (St to Q)
tPQ
6 11 µs
Propagation delay (St to StD)
tPStD
9 16 µs
OE = VDD
Output data setup (Q to StD)
tQStD
4.0
ms
Propagation delay (OE to Q), enable
Propagation delay (OE to Q), disable
tPTE
tPTD
50 60
300
ns
ns RL = 10 k, CL = 50 pF
Crystal clock frequency
fCLK
3.5759 3.5795
3.5831
MHz
Clock output (OSC2), capacitive load
CLO
30 pF
All voltages referenced to VSS unless otherwise noted. For typical values VDD = 5.0 V, VSS = 0 V, TA = 25°C, fCLK = 3.579545 MHz.
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Notes:
1. dBm = decibels above or below a reference power of 1 mW into a 600 W load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40 ms. Tone pause = 40 ms.
4. Nominal DTMF frequencies are used, measured at GS.
5. Both tones in the composite signal have an equal amplitude.
6. Bandwidth limited (0 to 3 kHz) Gaussian noise.
7. The precise dial tone frequencies are (350 and 440 Hz) ± 2%.
8. For an error rate of better than 1 in 10,000.
9. Referenced to lowest level frequency component in DTMF signal.
10. Minimum signal acceptance level is measured with specified maximum frequency deviation.
11. Input pins defined as IN+, IN-, and OE.
12. External voltage source used to bias VREF.
13. This parameter also applies to a third tone injected onto the power supply.
14. Referenced to Figure 4. Input DTMF tone level at -28 dBm.
40-406-00011, Rev. F
Page 6
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部品番号部品説明メーカ
M-8870

DTMF Receiver

Clare  Inc.
Clare Inc.
M-8870

DTMF Receiver

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M-8870-01

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M-8870-01SM

DTMF Receiver

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