PDF ISPPAC-CLK55xx Data sheet ( Hoja de datos )

Número de pieza	ISPPAC-CLK55xx
Descripción	In-System Programmable Clock Generator with Universal Fan-Out Buffer
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispClock™5500 Family In-System Programmable Clock Generator with Universal Fan-Out Buffer August 2004 Data Sheet Features ■ 10MHz to 320MHz Input/Output Operation ■ Low Output to Output Skew (<50ps) ■ Low Jitter Peak-to-Peak(<70ps) ■ Up to 20 Programmable Fan-out Buffers • Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, SSTL, LVDS, LVPECL • Programmable precision output impedance - 40 to 70Ω in 5Ω increments • Programmable slew rate • Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V ■ Fully Integrated High-Performance PLL • Programmable lock detect • Multiply and divide ratio controlled by - Input divider (5 bits) - Internal feedback divider (5 bits) - Five output dividers (5 bits) • Programmable On-chip Loop Filter ■ Precision Programmable Phase Adjustment (Skew) Per Output • 16 settings; minimum step size 195ps - Locked to VCO frequency • Up to +/- 12ns skew range • Coarse and ﬁne adjustment modes Product Family Block Diagram ■ Up to Five Clock Frequency Domains ■ Flexible Clock Reference Inputs • Programmable input standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL • Clock A/B selection multiplexer • Programmable precision termination ■ Four User-programmable Proﬁles Stored in E2CMOS® Memory • Supports both test and multiple operating conﬁgurations ■ Full JTAG Boundary Scan Test In-System Programming Support ■ Exceptional Power Supply Noise Immunity ■ Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges ■ 100-pin and 48-pin TQFP Packages ■ Applications • Circuit board common clock generation and distribution • PLL-based frequency generation • High fan-out clock buffer LOCK DETECT M * PHASE/ FREQUENCY FILTER DETECTOR N PLL CORE JTAG INTERFACE & E2CMOS MEMORY * Input Available only on ispClock 5520 BYPASS MUX VCO OUTPUT DIVIDERS V0 V1 V2 V3 V4 Multiple Profile Management Logic 0123 INTERNAL FEEDBACK PATH SKEW OUTPUT CONTROL DRIVERS OUTPUT ROUTING MATRIX © 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice. www.latticesemi.com 1 clk5500_04 1 page Lattice Semiconductor ispClock5500 Family Data Sheet Performance Characteristics – Power Supply Symbol Parameter Conditions Typ. ICCD Core Supply Current ispClock5510, fVCO = 640MHz ispClock5520, fVCO = 640MHz 100 130 ICCA Analog Supply Current fVCO = 640MHz 5.5 ICCO Output Driver Supply Current (per Bank) VCCO = 1.8V1, LVCMOS VCCO = 2.5V1, LVCMOS VCCO = 3.3V1, LVCMOS VCCO = 3.3V2, LVDS 13 18 24 7.5 VCCJ = 1.8V ICCJ JTAG I/O Supply Current (static) VCCJ = 2.5V VCCJ = 3.3V 200 300 300 1. Supply current consumed by each bank, both outputs active, 18pF load, 320MHz output frequency. 2. Supply current consumed by each bank, 100Ω/5pF differential load, 320MHz output frequency. Max. 110 150 7 15 24 35 8 300 400 400 Units mA mA mA mA µA DC Electrical Characteristics – Single-ended Logic Logic Standard VIL (V) Min. Max. VIH (V) Min. Max. LVTTL/LVCMOS 3.3V -0.3 0.8 2 3.6 LVCMOS 1.8V LVCMOS 2.5V -0.3 0.35VCCO 0.65VCCO -0.3 0.7 1.7 3.6 3.6 SSTL2 Class 1 -0.3 VREF - 0.18 VREF + 0.18 SSTL3 Class 1 -0.3 VREF - 0.2 VREF + 0.2 HSTL Class 1 -0.3 VREF - 0.1 VREF + 0.1 1. Speciﬁed for 50Ω internal series output termination. 2. Speciﬁed for 40Ω internal series output termination. 3. Speciﬁed for ≈20Ω internal series output termination. 3.6 3.6 3.6 VOL Max. (V) VOH Min. (V) 0.4 VCCO - 0.4 0.4 VCCO - 0.4 0.4 VCCO - 0.4 0.542 VCCO - 0.812 0.92 VCCO - 1.32 0.43 VCCO - 0.43 IOL (mA) 41 41 41 7.6 8 8 IOH (mA) -41 -41 -41 -7.6 -8 -8 DC Electrical Characteristics – LVDS Symbol Parameter Conditions VICM VTHD VIN VOH VOL VOD ∆VOD VOS ∆VOS ISA ISAB Common Mode Input Voltage Differential Input Threshold Input Voltage Output High Voltage Output Low Voltage Output Voltage Differential Change in VOD between H and L Output Voltage Offset RT = 100Ω RT = 100Ω RT = 100Ω Common Mode Output Voltage Change in VOS Between H and L Output Short Circuit Current Output Short Circuit Current VOD = 0V, Outputs Shorted to GND VOD = 0V, Outputs Shorted to Each Other Min. 0.05 ±100 0 — 0.9 250 — 1.125 — — — Typ. — — — 1.375 1.03 400 — 1.20 — — — Max. 2.35 — 2.4 1.60 — 480 50 1.375 50 24 12 Units V mV V V V mV mV V mV mA mA 5 5 Page Lattice Semiconductor ispClock5500 Family Data Sheet Timing Speciﬁcations Skew Matching Symbol Parameter tSKEW Output-output Skew Conditions Between any two identically conﬁgured and loaded outputs regardless of bank and output frequency Min. — Typ. — Max. 50 Units ps Programmable Skew Control Symbol Parameter Conditions Min. Typ. tSKRANGE SKSTEPS tSKSTEP tSKERR Skew Control Range1 Skew Steps per range Skew Step Size2 Skew Time Accuracy3 Fine Skew Mode, fVCO = 320 MHz Fine Skew Mode, fVCO = 640 MHz Coarse Skew Mode, fVCO = 320 MHz Coarse Skew Mode, fVCO = 640 MHz Fine Skew Mode, fVCO = 320 MHz Fine Skew Mode, fVCO = 640 MHz Coarse Skew Mode, fVCO = 320 MHz Coarse Skew Mode, fVCO = 640 MHz Fine skew mode Coarse skew mode — — — — — — — — — — — 5.86 2.93 11.72 5.86 16 390 195 780 390 30 50 1. Skew control range is a function of VCO frequency (fVCO). In ﬁne skew mode TSKRANGE = 15/(8 x fVCO). In coarse skew mode TSKRANGE = 15/(4 x fVCO). 2. Skew step size is a function of VCO frequency (fVCO). In ﬁne skew mode TSKSTEP = 1/(8 x fVCO). In coarse skew mode TSKSTEP = 1/(4 x fVCO). 3. Only applicable to outputs with non-zero skew settings. Max. — — — — — — — — — — — Units ns ps ps Control Functions Symbol Parameter tDIS/OE Delay Time, OEX or OEY to Output Disabled/ Enabled tDIS/GOE tSUSGATE Delay Time, GOE to Output Disabled/Enabled Setup Time, SGATE to Output Clock Start/ Stop tPLL_RSTW PLL Reset Pulse Width tHPS_RST Hold time for RESET past change in PS[0..1] 1. Output clock cycles for the particular output being controlled. Conditions Min. — — 3 15 20 Typ. 10 10 — — — Max. Units 20 ns 20 ns — cycles1 — µs — ns Figure 6. RESET and Proﬁle Select Timing PS[0..1] RESET tHPS_RST tPLL_RSTW 11 11 Page

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