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Número de pieza | IN74HC165 | |
Descripción | 8-Bit Serial or Parallel-Input/Serial-Output Shift Register High-Performance Silicon-Gate CMOS | |
Fabricantes | ETC | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de IN74HC165 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
No Preview Available ! TECHNICAL DATA
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The IN74HC165 is identical in pinout to the LS/ALS165. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs
from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Serial Shift/ Parallel Load input is
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load input is high, the data is loaded serially on the
rising edge of either Clock or Clock Inhibit (see the Function Table).
The 2-input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to
act as a clock inhibit.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
IN74HC165
ORDERING INFORMATION
IN74HC165N Plastic
IN74HC165D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16=VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Internal Stages Output
Serial Shift/ Clock Clock SA A-H QA QB-QG
Parallel Load
Inhibit
QH
L
H
X X a...h a
b-g
h
H
L LX
L QAn-QFn QGn
H
L HX
H QAn-QFn QGn
HL
HL
LX
HX
L QAn-QFn QGn
H QAn-QFn QGn
H X H XX
no change
H H X XX
H L L XX
X = Don’t Care
QAn-QFn = Data shifted from the preceding stage
no change
Operation
Asynchronous Parallel Load
Serial Shift via Clock
Serial Shift via Clock
Inhibit
Inhibited Clock
No Clock
228
1 page IN74HC165
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
VCC
V
tSU Minimum Setup Time, Parallel 2.0
Data Inputs to Serial
4.5
Shift/Parallel Load (Figure 4) 6.0
tSU Minimum Setup Time, Input 2.0
SA to Clock (or Clock Inhibit) 4.5
(Figure 5)
6.0
tSU Minimum Setup Time, Serial 2.0
Shift/Parallel Load to Clock
4.5
(or Clock Inhibit) (Figure 6)
6.0
tSU Minimum Setup Time, Clock 2.0
to Clock Inhibit (Figure 7)
4.5
6.0
th Minimum Hold Time, Serial 2.0
Shift/Parallel Load to Parallel 4.5
Data Inputs (Figure 4)
6.0
th Minimum Hold Time, Clock 2.0
(or Clock Inhibit) to Input SA 4.5
(Figure 5)
6.0
th Minimum Hold Time, Clock 2.0
(or Clock Inhibit) to Serial
4.5
Shift/Parallel Load (Figure 6) 6.0
trec Minimum Recovery Time,
Clock to Clock Inhibit
(Figure 7)
2.0
4.5
6.0
tw Minimum Pulse Width, Clock 2.0
(or Clock Inhibit) (Figure 1)
4.5
6.0
tw Minimum Pulse Width, Serial 2.0
Shift/Parallel Load (Figure 2) 4.5
6.0
tr, tf Maximum Input Rise and Fall 2.0
Times (Figure 1)
4.5
6.0
Guaranteed Limit
25 °C to
-55°C
≤85°C
≤125°C
100 125 150
20 25 30
17 21 26
100 125 150
20 25 30
17 21 26
100 125 150
20 25 30
17 21 26
100 125 150
20 25 30
17 21 26
555
555
555
555
555
555
555
555
555
100 125 150
20 25 30
17 21 26
80 100 120
16 20 24
14 17 20
80 100 120
16 20 24
14 17 20
1000
500
400
1000
500
400
1000
500
400
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
232
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet IN74HC165.PDF ] |
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