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PDF UPA2756GR Data sheet ( Hoja de datos )
| Número de pieza | UPA2756GR | |
| Descripción | SWITCHING N- AND P-CHANNEL POWER MOS FET | |
| Fabricantes | NEC | |
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA2756GR
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
The µ PA2756GR is Dual N-channel MOS Field Effect
Transistor designed for switching applications.
FEATURES
• Low on-state resistance
RDS(on)1 = 105 mΩ MAX. (VGS = 10 V, ID = 2.0 A)
RDS(on)2 = 150 mΩ MAX. (VGS = 4.0 V, ID = 2.0 A)
• Low Ciss: Ciss = 260 pF TYP.
• Built-in G-S protection diode against ESD
• Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
µ PA2756GR
PACKAGE
Power SOP8
PACKAGE DRAWING (Unit: mm)
85
14
5.37 MAX.
1 : Source 1
2 : Gate 1
7, 8: Drain 1
3 : Source 2
4 : Gate 2
5, 6: Drain 2
6.0 ±0.3
4.4
0.8
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
0.5 ±0.2
0.10
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
60
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) Note1
Drain Current (pulse) Note2
Total Power Dissipation (1 unit) Note1
Total Power Dissipation (2 units) Note1
VGSS
ID(DC)
ID(pulse)
PT1
PT2
±20
±4.0
±16
1.6
2.0
Channel Temperature
Tch 150
Storage Temperature
Single Avalanche Current Note3
Single Avalanche Energy Note3
Repetitive Avalanche Energy Note4
Tstg −55 to +150
IAS 4.0
EAS 1.6
EAR 1.6
V
V
A
A
W
W
°C
°C
A
mJ
mJ
EQUIVALENT CIRCUIT
Drain 1
Drain 2
Gate 1
Body
Diode Gate 2
Body
Diode
Gate
Protection Source 1
Diode
Gate
Protection Source 2
Diode
Notes 1. Mounted on ceramic substrate of 2000 mm2 x 2.2 mm
2. PW ≤ 10 µs, Duty Cycle ≤ 1%
3. Starting Tch = 25°C, VDD = 30 V, RG = 25 Ω, VGS = 20 → 0 V
4. IAR ≤ 4.0 A, Tch ≤ 150°C
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage exceeding
the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G17407EJ1V0DS00 (1st edition)
Date Published January 2005 NS CP(K)
Printed in Japan
2005
1 page  
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
200
180 ID = 2.0 A
Pulsed
160
140 VGS = 4.0 V
120
100
80 10 V
60
40
20
0
-50 -25 0 25 50 75 100 125 150 175
Tch - Channel Temperature - °C
1000
100
10
SWITCHING CHARACTERISTICS
VDD = 30 V
VGS = 10 V
RG = 10 Ω
td(off)
tf
td(on)
tr
1
0.1
1 10
ID - Drain Current - A
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
100
Pulsed
10 VGS = 10 V
4.0 V
1
0V
100
0.1
0.01
0
0.5 1
VF(S-D) - Source to Drain Voltage - V
1.5
µ PA2756GR
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
1000
Ciss
100
Coss
10
Crss
VGS = 0 V
f = 1 MHz
1
0.1
1
10 100
VDS - Drain to Source Voltage - V
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
60 12
ID = 4.0 A
50 VDD = 48 V
30 V
10
40
12 V
8
30 6
20
VGS
4
10
0
0
VDS
12345
QG - Gate Charge - nC
6
2
0
7
1000
REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
VGS = 0 V
di/dt = 100 A/µs
100
10
1
0.1
1 10
IF - Diode Forward Current - A
100
Data Sheet G17407EJ1V0DS
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet UPA2756GR.PDF ] | |
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