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PDF DS1808 Data sheet ( Hoja de datos )
| Número de pieza | DS1808 | |
| Descripción | Dual Log Digital Potentiometer | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DS1808 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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DS1808
Dual Log Digital Potentiometer
www.maxim-ic.com
FEATURES
§ Two 32-position log-tapers
§ 60dB attenuation range:
–1dB per step (12 taps)
–2dB per step (12 taps)
–3dB per step (8 taps)
–90dB low-end attenuation
§ 2-Wire Interface Control
§ Power Supply: Dual ±12V
§ Maximum Voltage Across Potentiometers:
±12V
§ Standard Resistance Value: 45kW
§ Packages: 16-Pin SOIC
§ Operating Temperature: -40oC to +85oC
PIN ASSIGNMENT
GND
A2
A1
VB
A0
W0
L0
H0
1
2
3
4
5
6
7
8
16 VDD
15 VCC
14 SCL
13 SDA
12 CE
11 W
10 H1
9 L1
16-Pin SOIC (150-mil)
ORDERING INFORMATION
DS1808Z-050
16-Pin SOIC -40ºC to
+85ºC 45kΩ
DS1808Z-050/T&R 16-Pin SOIC -40ºC to
+85ºC 45kΩ
PIN DESCRIPTION
VCC
VB
VDD
H0, H1
L0, L1
W0, W1
SDA
- +12V Supply
- -12V Supply (substrate bias)
- 5V Digital Supply
- High-end Terminals
- Low-end Terminals
- Wiper Terminals
- 2-Wire Serial Data Input/Output
SCL - 2-Wire Clock Input
/CE - 2-Wire Interface Enable
GND
- Ground
A0, A1, A2 - Address Pins
DESCRIPTION
The DS1808 is a dual-channel, digitally controlled, log-taper potentiometer. Each potentiometer is
comprised of 32 wiper terminal positions plus a mute position. The device has three accessible
potentiometer terminals that include the high-side terminal (H), the low-side terminal (L), and the wiper
terminal (W). The resolution of the DS1808 is shown in Figure 8 and represents 1dB per step for the first
12 taps, 2dB per step for the next 12 taps and 3dB per step for the bottom 8 taps, providing a total
attenuation range of 60dB. The mute position of the DS1808 provides greater than 90dB of attenuation.
The wiper position on the resistor ladder is selected via a 6-bit register, whose value is controlled by the
industry-standard 2-wire interface. The interface consists of two control signals: SDA and SCL. The
DS1808 is available in a standard 45kW resistor value. The DS1808 is specified to operate over the
industrial temperature range (-40oC to +85oC) and is available in the 16-pin SOIC package. The DS1808
was designed for low-cost, stereo volume control applications. The device is specified to operate from
±12V ±10% supplies and accept a maximum input signal range of ±12V.
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072601
1 page  
2-WIRE SERIAL PROTOCOL
DS1808
The following bus protocol has been defined:
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain high.
Start data transfer: A change in the state of the data line from high to low while the clock is high
defines a start condition.
Stop data transfer: A change in the state of the data line from low to high while the clock line is high
defines the stop condition.
Data valid: The state of the data line represents valid data when, after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line can be changed during
the low period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3 detail how
data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit, two types of
data transfer are possible.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of
data bytes transferred between start and stop conditions is not limited and is determined by the master
device. The information is transferred byte-wise and each receiver acknowledges with a 9th bit.
Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1808 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an “acknowledge” after the
reception of each byte. The master device must generate an extra clock pulse that is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable the master to generate the stop condition.
1. The following occurs when data is transferred from a master transmitter to a slave receiver. The first
byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The
slave returns an acknowledge bit after each received byte.
2. The following occurs when data is transferred from a slave transmitter to a master receiver. The
master transmits the first byte (the command/control byte) to the slave. The slave then returns an
acknowledge bit. Next, follows a number of data bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowledge” can be returned.
5 of 17
5 Page 
ABSOLUTE MAXIMUM RATINGS*
Voltage on All Pins (except /CE, SDA, SCL,
A0, A1, and A2) Relative to Ground
Voltage on Pins /CE, SDA, SCL, A0, A1, and A2
Operating Temperature
Storage Temperature
Soldering Temperature
VB - 0.3V to VCC + 0.3V
GND - 0.3V to VDD + 0.3V
-40°C to +85°C
-55°C to +125°C
See J-STD-020A specification
DS1808
*This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
SYMBOL MIN
TYP
Analog Supply Voltage
VCC +4.5
Substrate Bias Voltage
VB -13.2
Digital Supply Voltage
VDD 4.5
Resistor Inputs
L,H,W
VB
MAX
+13.2
0
5.5
VCC
(-40°C to +85°C)
UNITS NOTES
V 1, 3
V3
V3
V
DC ELECTRICAL CHARACTERISTICS
(-40°C to +85°C/VCC, VB=±5V to ±13.2V/VDD=4.5V to 5.5V)
PARAMETER
SYMBOL CONDITION MIN TYP MAX UNITS NOTES
Supply Current
Active
Input Leakage
Input Logic 1
ICC
ILI
VIH
-1
0.7VDD
2
+1
VDD +
0.3V
mA
mA
V
12, 13
2
Input Logic 0
VIL
GND-0.3
0.8 V
2
Power Up Time
(Port Active)
Standby Current
(VCC, VB)
Active Supply
Current (VB)
tPU
ISTBY
±8V
±12V
1 ms
15 mA
25
4
2.0 mA 12, 13
11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet DS1808.PDF ] | |
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