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PDF UM82C55A Data sheet ( Hoja de datos )
| Número de pieza | UM82C55A | |
| Descripción | CMOS PROGRMMABLE PERIPHERAL INTERFACE | |
| Fabricantes | UMC | |
| Logotipo |  |
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SUMO
UM82C55A
CMOS Programmable
Peripheral Interface
Features
• Pin compatible with NMOS 8255A
• 24 programmable I/O pins
• Fully TTL compatible
• Bus-hold circuitry on all I/O ports eliminates pull-up
resistors
• High speed, no "wait state" operation with 8M Hz
80C86
• Direct bit set/reset capabi lity
• Enhanced control word read capabi lity
• Single 5V power supply
• 2.5mA drive capabi lity on all I/O port outputs
• Low standby power -ICCSB = 10llA
General Description
The UM82C55A is a high performance CMOS version of the
industry standard 8255A and is manufactured using a
selfaligned silicon gate CMOS process. It is a general
purpose programmable I/O device which may be used with
many different microprocessors. There are 24 I/O pins
which may be individually programmed in 2 groups of 12
and used in 3 major modes of operation. The high
performance of the UM82C55A make it compatible with
microprocessors such as the 8086, 8048, 8051.
Static CMOS circuit design insures low operating power.
TTL compatibility of V 1H =2.0 volts over the industrial
temperature range and bus hold circuitry eliminate the
need for pull-up resistors.
Pin Configuration
Block Diagram
PA3
PA2
PAl
PAO
Ro
cs
GNo
Al
AO
PC7
PC6
PC5
PC4
PCO
PCl
PC2
PC3
PBO
PBl
PB2
PA4
PA5
PA6
PA7
WR
RESET
DO
01
02
03
04
05
06
07
VCC
PB7
PB6
PB5
PB4
PB3
POWER { _ 5 V
SUPPLIES _ G N D
D7·DO
I/O
PA7·PAQ
I/O
C7·PC4
I/O
PC3·PCO
PIN NAMES
0,-00
RESET
cs
AO.Al
PA7·PAQ
PB7·PBO
DATA BUS IBI·
DIRECTIONAL)
RESET INPUT
CHIPSELECT
READ INPUT
WRITE INPUT
PORT ADDRESS
PORT A IBIT).
PORTB IBIT)
PC7·PCO
GND
PORTC IBIT!
+5 VOLTS
o VOLTS
I/O
PB7·PBO
7-109
1 page  
MODE 1 (Strobe Output)
UM82C55A
MODE 2 (BIDIRECTIONAL)
DATA FROM
8080 TO 8255
STB
IBF
PERIPHERAL
BUS - •• -- •• - •• - ••• - •• - •• -
DATA FROM
8255 TO PERIPHERAL
DATA FROM
8255 TO 8080
Note: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = ISF • MASK· STB •
RD + OBF • MASK· ACK • WR)
WRITE TIMING
AO_1CS~
- - - - J l = = t A w - - -1
------XDATA BUS
1
X-
--! '~-tW-A---
IX=:
~gtDW_'tWD:j
WR
tww
READ TIMING
- - y -AO_1CS
r
_ - j::: tAR :m-fR,""A..:.~_=======
RD tRR
itRD OF
DATA BUS
HIGH IMPEDANCE : VALID I HIGH IMPEDANCE
!,
7-113
5 Page 
CONTROL WORD #8
07 06 05 04 03 02 01 00
11101011101010101
07-00
A~PA7-PAO
UM82C55A
4 PC7-PC4
C{
4 PC3-PCO
B 8 PB7-PBO
CONTROL WORD #12
07 06 05 04 03 02 01 00
UMB2C55A
..07-00
8
A
UM82C55A
C{ L4
~
a
4
B ~8
PA7-PAO
PC7-PC4
PC3-PCO
PB7-PBO
CONTROL WORD #9
07 06 05 04 03 02 01 00
11101011101010111
07-00
A
UM82C55A
c{
B
8 PA7-PAO
4 PC7-PC4
4 PC3-PCO
8 PB7-PBO
CONTROL WORD #10
07 06 05 04 03 02 01 00
11101011101011101
07-00
A
UM82C55A
c{
B
8 PA7-PAO
4
PC7-PC4
4 PC3-PCO
8 PB7-PBO
CONTROL WORD #11
07 06 05 04 03 02 01 DO
11101011101011111
07-~0
A
UM82C55A
c{
B
8 PA7-PAO
4 PC7-PC4
4
PC3-PCO
8 PB7-PBO
CONTROL WORD #13
07 06 05 04 03 02 01 00
.07-00
A
~
8
UM82C55A
. C{ ,4
L4
8
B
PA7-PAO
PC7-PC4
PC3-PCO
PB7-PBO
CONTROL WORD #14
07 06 05 04 03 02 01 00
..07-00
A
UM82C55A
.. c{
8
-L4
4
B~
8
PA7-PAO
PC7-PC4
PC3-PCO
PB7-PBO
CONTROL WORD #15
07 06 05 04 03 02 01 DO
07-00
A
UM82C55A
c{
~
8
4
4
B ~8
PA7-PAP
PC7-PC4
PC3-PCO
PB7-PBO
7-119
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet UM82C55A.PDF ] | |
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