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UBA2033のメーカーはNXP Semiconductorsです、この部品の機能は「HF full bridge driver IC」です。 |
部品番号 | UBA2033 |
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部品説明 | HF full bridge driver IC | ||
メーカ | NXP Semiconductors | ||
ロゴ | |||
このページの下部にプレビューとUBA2033ダウンロード(pdfファイル)リンクがあります。 Total 20 pages
INTEGRATED CIRCUITS
DATA SHEET
UBA2033
HF full bridge driver IC
Product specification
2002 Oct 08
1 Page Philips Semiconductors
HF full bridge driver IC
BLOCK DIAGRAM
Product specification
UBA2033
handbook, full pagewidth
6
HV
14
SGND
VDD
RC
9
13
10
SU
12
BD
−LVS EXTDR
12
+LVS
3
STABILIZER
UVLO
OSCILLATOR
LOGIC SIGNAL
GENERATOR
2
HIGH VOLTAGE
LEVEL SHIFTER
UBA2033TS
HIGHER LEFT
DRIVER
HIGHER RIGHT
DRIVER
LOWER RIGHT
DRIVER
16
FSL
15
GHL
17 SHL
27
FSR
28
GHR
26 SHR
23
GLR
1.29 V
bridge disable
LOGIC
11
DD
LOW VOLTAGE
LEVEL SHIFTER
LOWER LEFT
DRIVER
20
GLL
4, 5, 7, 8, 18,
19, 22, 24, 25
21
n.c. PGND MBL457
Fig.1 Block diagram.
2002 Oct 08
3
3Pages Philips Semiconductors
HF full bridge driver IC
Product specification
UBA2033
’Dead time’ can be increased by adding a resistor (for
slowly turning on the full bridge power FETs) and a diode
(for quickly turning off the full bridge power FETs) in
parallel, both in series with the gate drivers (see Fig.3).
Divider function
If pin DD = SGND, then the divider function is
enabled/present. If the divider function is present there is
no direct relation between the position of the bridge output
and the status of pin EXTDR.
Start-up delay
Normally, the circuit starts oscillating as soon as pin VDD or
HV reaches the level of release power drive. At this
moment the gate drive voltage is equal to the voltage on
pin VDD for the low side transistors and VDD − 0.6 V for the
high side transistors. If this voltage is too low for sufficient
drive of the MOSFETs the release of the power drive can
be delayed via pin SU.
A simple RC filter (R between pins VDD and SU;
C between pins SU and SGND) can be used to make a
delay, or a control signal from a processor can be used.
Bridge disable
The bridge disable function can be used to switch off all the
MOSFETs as soon as the voltage on pin BD exceeds the
bridge disable voltage (1.29 V). The bridge disable
function overrules all the other states.
Table 1 Logic table; note 1
DEVICE
STATUS
Start-up state
Oscillation state
BD
HIGH
LOW
HIGH
LOW
LOW
LOW
INPUTS
SU
X
X
X
LOW
HIGH
DD
X
X
X
X
HIGH
HIGH
LOW
EXTDR
X
X
X
X
HIGH
LOW
LOW
LOW-to-HIGH
HIGH
HIGH-to-LOW
GHL
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
OUTPUTS
GHR
LOW
LOW
LOW
LOW
HIGH
LOW
LOW
GLL
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
GLR
LOW
HIGH
LOW
HIGH
LOW
HIGH
HIGH
LOW
Note
1. X = don’t care
a) BD, SU and DD logic levels are with respect to SGND
b) EXTDR logic levels are with respect to V−LVS
c) GHL logic levels are with respect to SHL
d) GHR logic levels are with respect to SHR
e) GLL and GLR logic levels are with respect to PGND
f) If pin DD = LOW the bridge enters the state (oscillation state and pin BD = LOW and pin SU = HIGH) in the
pre-defined position pin GHL and pin GLR = HIGH and pin GLL and pin GHR = LOW.
2002 Oct 08
6
6 Page | |||
ページ | 合計 : 20 ページ | ||
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PDF ダウンロード | [ UBA2033 データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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