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PDF MX29LV161 Data sheet ( Hoja de datos )
| Número de pieza | MX29LV161 | |
| Descripción | 16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX29LV161T/B
16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 2,097,152 x 8/1,048,576 x 16 switchable
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 70/90ns
• Low power consumption
- 20mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x31)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
• Status Reply
- Data polling & Toggle bit for detection of program and
erase operation completion.
• Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase operation completion.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Tempoary sector unprotect allows code changes in
previously locked sectors.
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 2.3V
• Package type:
- 44-pin SOP
- 48-pin TSOP
- 48 Ball CSP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
GENERAL DESCRIPTION
The MX29LV161T/B is a 16-mega bit Flash memory or-
ganized as 2M bytes of 8 bits or 1M words of 16 bits.
MXIC's Flash memories offer the most cost-effective
and reliable read/write non-volatile random access
memory. The MX29LV161T/B is packaged in 44-pin
SOP, 48-pin TSOP, and 48CSP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29LV161T/B offers access time as fast
as 70ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV161T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV161T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV161T/B uses a 2.7V~3.6V VCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM0855
REV. 1.0, SEP. 24, 2001
1
1 page  
BLOCK DIAGRAM
MX29LV161T/B
CE
OE
WE
RESET
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
A0-A19
ADDRESS
LATCH
AND
BUFFER
MX29LV161T/B
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
STATE
REGISTER
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
PROGRAM
DATA LATCH
COMMAND
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
P/N:PM0855
REV. 1.0, SEP. 24, 2001
5
5 Page 
MX29LV161T/B
the Flash memory.
If RESET is asserted during a program or erase
operation, the RY/BY pin remains a "0" (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
sysytem can thus monitor RY/BY to determine whether
the reset operation is complete. If RESET is asserted
when a program or erase operation is commpleted within
a time of tREADY (not during Embedded Algorithms).
The system can read data tRH after the RESET pin
returns to VIH.
Refer to the AC Characteristics tables for RESET
parameters and to Figure 22 for the timing diagram.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SILICON-ID READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage(VID). However, multiplexing high voltage
onto address lines is not generally desired system de-
sign practice.
The MX29LV161T/Bcontains a Silicon-ID-Read opera-
tion to supple traditional PROM programming methodol-
ogy. The operation is initiated by writing the read silicon
ID command sequence into the command register. Fol-
lowing the command write, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer code of C2H/00C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of C4H/22C4H for MX29LV161T, 49H/2249H for
MX29LV161B.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H
or sector erase command 30H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 7), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE or CE pulse, whichever happens first in the
command sequence and terminates when the data on
Q7 is "1" and the data on Q6 stops toggling for two con-
secutive read cycles, at which time the device returns
to the Read mode.
P/N:PM0855
REV. 1.0, SEP. 24, 2001
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX29LV161.PDF ] | |
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