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PDF ST20Cx Data sheet ( Hoja de datos )
| Número de pieza | ST20Cx | |
| Descripción | Instruction Set Reference Manual | |
| Fabricantes | ST Microelectronics | |
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ST20C2/C4 Core
Instruction Set
Reference Manual
72-TRN-273-01 January 1996
®
1 page  
1 Introduction
This manual provides a summary and reference to the ST20 instruction set for C2 and
C4 cores. The instructions are listed in alphabetical order, one to a page. Descriptions
are presented in a standard format with the instruction mnemonic and full name of the
instruction at the top of the page, followed by these categories of information:
• Code: the instruction code;
• Description: a brief summary of the purpose and behavior of the instruction;
• Definition: a more complete description of the instruction, using the notation
described below in section 1.7;
• Error signals: a list of errors and other signals which can occur;
• Comments: a list of other important features of the instruction;
• See also: for some instructions, a cross reference is provided to other instruc-
tions with a related function.
These categories are explained in more detail below, using the add instruction as an
example.
1.1 Instruction name
The header at the top of each page shows the instruction mnemonic and, on the right,
the full name of the instruction. For primary instructions the mnemonic is followed by
‘n’ to indicate the operand to the instruction; the same notation is used in the
description to show how the operand is used.
1.2 Code
For secondar y instructions the instruction ‘operation code’ is shown as the memory
code — the actual bytes, including any prefixes, which are stored in memory. The
value is given as a sequence of bytes in hexadecimal, decoded left to right. The codes
are stored in memory in ‘little-endian’ format — with the first byte at the lowest
address.
For primary instructions the code stored in memory is determined partly by the value
of the operand to the instruction. In this case the op-code is shown as ‘Function x’
where x is the function code in the last byte of the instruction. For example, adc (add
constant) is shown as ‘Function 8’.
Example
The entry for the add instruction is:
Code: F5
5/212
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5 Page 
1.7.6 On-chip peripherals
On-chip peripherals may have memory-mapped registers in the address range
PeripheralStart to PeripheralEnd. Access to these registers is represented in the
following way:
PeripheralByte[address] references an 8-bit peripheral register
PeripheralSixteen[address] references a 16-bit peripheral register
PeripheralWord[address] references a 32-bit peripheral register
For all of these, the state of the peripheral referenced is that before the instruction if
the function is used without a prime (e.g. PeripheralWord[]), and that after the
instruction if the function is used with a prime (e.g. PeripheralWord′[]).
For example, writing a value given by an expression, expr, to the register at address
addr is represented by:
PeripheralWord′[addr] ← expr
and reading a word from a peripheral is achieved by:
Areg′ ← PeripheralWord[addr]
1.8 Block move registers
A group of registers is used in the implementation of block moves. These are referred
to as the ‘block move registers’ and include Move2dBlockLength, Move2dDestStride,
and Move2dSourceStride.
1.9 Constants
A number of data structures have been defined in this book. Each compr ises a
number of data slots that are referenced by name in the text and the following
instructions descriptions.
These data structures is listed in Table 1.2 to Table 1.4.
word offset
0
-1
-2
-3
-3
-4
-5
slot name
pw.Temp
pw.Iptr
pw.Link
pw.Pointer
pw.State
pw.TLink
pw.Time
purpose
slot used by some instructions for storing temporary values
the instruction pointer of a descheduled process
the address of the workspace of the next process in scheduling list
saved pointer to communication data area
saved alternative state
address of the workspace of the next process on the timer list
time that a process on a timer list is waiting for
Table 1.1 Process workspace data structure
11/212
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