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PDF ST20-GP1 Data sheet ( Hoja de datos )
| Número de pieza | ST20-GP1 | |
| Descripción | GPS PROCESSOR | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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® ST20-GP1
FEATURES
s Application specific features
• 12 channel GPS correlation DSP hardware
and ST20 CPU (for control and position calu-
culations) on one chip
• no TCXO required
• RTCA-SC159 / WAAS / EGNOS supported
s GPS performance
• accuracy
- stand alone
with SA on <100m, SA off <30m
- differential <1m
- surveying <1cm
• time to first fix
- autonomous start 90s
- cold start 45s
- warm start 7s
- obscuration 1s
s 32-bit ST20 CPU
• 16/33 MHz processor clock
• 25 MIPS at 33 MHz
• fast integer/bit operations
s 4 Kbytes on-chip SRAM
• 130 Mbytes/s maximum bandwidth
s Programmable memory interface
• 4 separately configurable regions
• 8/16-bits wide
• support for mixed memory
• 2 cycle external access
s Serial communications
• Programmable UART (ASC)
• OS-Link
s Vectored interrupt subsystem
• 2 dedicated interrupt pins
• 5 levels of interrupt
s Power management
• low power operation
• power down modes
s Professional toolset support
• ANSI C compiler and libraries
• INQUEST advanced debugging tools
s Technology
• Static clocked 50 MHz design
• 3.3 V, sub micron technology
s 100 pin PQFP package
GPS PROCESSOR
ENGINEERING DATA
GPS
radio
12 channel GPS
hardware DSP
ST20-GP1
ST20
CPU
Low
power
controller
Interrupt
controller
Real time
clock/calendar
4K
SRAM
Programmable
memory
interface
Serial
communications
2 UART (ASC)
1 OS-Link
Parallel
input/output
Byte-wide
parallel port
... 6
... 8
RAM
ROM/
FLASH
APPLICATIONS
s Global Positioning System (GPS) receivers
s Car navigation systems
s Fleet management systems
s Time reference for telecom systems
October 1996
The information in this datasheet is subject to change
1/116
42 1672 02
1 page  
ST20-GP1
1 Introduction
The ST20-GP1 is an application-specific single chip micro using the ST20 CPU with
microprocessor style peripherals added on-chip. It incorporates DSP hardware for processing the
signals from GPS (Global Positioning System) satellites.
The twelve channel GPS correlation DSP hardware is designed to handle twelve satellites, two of
which can be initialized to support the RTCA-SC159 specification for WAAS (Wide Area
Augmentation Service) and EGNOS (European Geostationary Navigation Overlay System)
services.
The ST20-GP1 has been designed to minimize system costs and reduce the complexity of GPS
systems. It offers all hardware DSP and microprocessor functions on one chip. Whilst the entire
analogue section, RF and clock generation are available on a companion chip. Thus, with the
addition of a ROM and a RAM chip, a complete GPS system is possible using just four chips, see
Figure 1.1.
Antenna
ST20-GP1
Radio
Single chip
DSP
ASIC
Low
cost
crystal
No TCXO
CPU
Watchdog
timer
UART
Real
time
clock
Driver
(optional)
Parallel I/O
ROM
RAM
Figure 1.1 GPS system
The ST20-GP1 supports large values of frequency offset, allowing the use of a very low cost
oscillator, thus saving the cost of a Temperature Controlled Crystal Oscillator (TCXO).
The CPU and software have access to the part-processed signal to enable accelerated acquisition
time.
The ST20-GP1 can implement the GPS digital signal processing algorithms using less than 50% of
the available CPU processing power. This leaves the rest available for integrating OEM application
functions such as route-finding, map display and telemetry. A hardware microkernel in the ST20
5/116
®
5 Page 
ST20-GP1
3 Digital signal processing module
The ST20-GP1 chip includes 12 channel GPS correlation DSP hardware. It is designed to handle
twelve satellites, two of which can be initialized to support the RTCA-SC159 specification.
The digital signal processing (DSP) module extracts GPS data from the incoming IF (Intermediate
Frequency) data. There are a number of stages of processing involved; these are summarized
below and in Figure 3.1. After the 12 pairs of hardware correlators, the data for all channels are
time division multiplexed onto the appropriate internal buses (i.e. values for each channel are
passed in sequence, for example: I1, Q1, I2, Q2 ... I12, Q12, I1, Q1).
4 MHz IF
input
frequency
converter A
data
sampler
I correlator
(x 12)
Q correlator
(x 12)
frequency
converter B
DMA
interface
accumulator
Pseudo random
noise sequence
generator
(x 12)
Numerically
controlled
oscillator
ST20 CPU accessible
registers
Figure 3.1 DSP module block diagram
The main stages of processing are as follows:
Data sampling
This stage removes any meta-stability caused by the asynchronous input data coming from an
analogue source (the radio receiver). The data at this point consists of a carrier of nominally
4.092 MHz with a bandwidth of approximately ±1 MHz.
This stage is common to all 12 channels.
Frequency conversion (A)
The first frequency converter mixes the sampled IF data with the (nominal) 4.092 MHz signal. This
is done twice with a quarter cycle offset to produce I and Q (In-phase and Quadrature) versions of
the data at nominal zero centre frequency (this can actually be up to ±132 KHz due to errors such
11/116
®
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