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PM49FL004 の電気的特性と機能

PM49FL004のメーカーはProgrammable Microelectronicsです、この部品の機能は「2 Mbit / 4 Mbit 3.3 Volt-only Fimware Hub / LPC Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 PM49FL004
部品説明 2 Mbit / 4 Mbit 3.3 Volt-only Fimware Hub / LPC Flash Memory
メーカ Programmable Microelectronics
ロゴ Programmable Microelectronics ロゴ 




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PM49FL004 Datasheet, PM49FL004 PDF,ピン配置, 機能
PMC
Pm49FL002 / Pm49FL004
2 Mbit / 4 Mbit 3.3 Volt-only Firmware Hub/LPC Flash Memory
FEATURES
• Single Power Supply Operation
- Low voltage range: 3.0 V - 3.6 V
• Standard Intel Firmware Hub/LPC Inter-
face
- Read compatible to Intel® 82802 Firmware
Hub devices
- Conforms to Intel LPC Interface Specification
Revision 1.1
• Memory Configuration
- Pm49FL002: 256K x 8 (2 Mbit)
- Pm49FL004: 512K x 8 (4 Mbit)
Cost Effective Sector/Block Architecture
- Pm49FL002: Sixty-four uniform 4 Kbyte
sectors, or sixteen uniform 16 Kbyte blocks
(sector group)
- Pm49FL004: One hundred and twenty-eight
uniform 4 Kbyte sectors, or eight uniform 64
Kbyte blocks (sector group)
Top Boot Block
- Pm49FL002: 16 Kbyte top Boot Block
- Pm49FL004: 64 Kbyte top Boot Block
Automatic Erase and Program Operation
- Build-in automatic program verification for
extended product endurance
- Typical 25 µs/byte programming time
- Typical 50 ms sector/block/chip erase time
Two Configurable Interfaces
- In-System hardware interface: Auto detection
of Firmware Hub (FWH) or Low Pin Count
(LPC) memory cycle for in-system read and
write operations
- Address/Address-Multiplexed (A/A Mux)
interface for programming on EPROM Pro-
grammers during manufacturing
Firmware HUB (FWH)/Low Pin Count
(LPC) Mode
- 33 MHz synchronous operation with PCI bus
- 5-signal communication interface for in-
system read and write operations
- Standard SDP Command Set
- Data# Polling and Toggle Bit features
- Register-based read and write protection for
each block (FWH mode only)
- 4 ID pins for multiple Flash chips selection
(FWH mode only)
- 5 GPI pins for General Purpose Input Register
- TBL# pin for hardware write protection to Boot
Block
- WP# pin for hardware write protection to whole
memory array except Boot Block
Address/Address Multiplexed (A/A Mux)
Mode
- 11-pin multiplexed address and 8-pin data I/O
interface
- Supports fast programming on EPROM
programmers
- Standard SDP Command Set
- Data# Polling and Toggle Bit features
Lower Power Consumption
- Typical 2 mA active read current
- Typical 7 mA program/erase current
High Product Endurance
- Guarantee 100,000 program/erase cycles per
single sector (preliminary)
- Minimum 20 years data retention
Compatible Pin-out and Packaging
- 32-pin (8 mm x 14 mm) VSOP
- 32-pin PLCC
- Optional lead-free (Pb-free) package
Hardware Data Protection
Programmable Microelectronics Corp.
PMC and P-Flash are registered trademark of Programmable Microelectronics Corporation.
Intel is a registered trademark of Intel Corporation.
1
Issue Date: December, 2003 Rev:1.4

1 Page





PM49FL004 pdf, ピン配列
PMC
CONNECTION DIAGRAMS
Pm49FL002 / 004
FWH
GPI1
GPI0
WP#
TBL#
ID3
ID2
ID1
ID0
FWH0
LPC
GPI1
GPI0
WP#
TBL#
RES
RES
RES
RES
LAD0
A/A Mux
A7 5
43
A/A Mux LPC FWH
2 1 32 31 30
29 IC
IC
IC
A6 6
28 GND GND
GND
A5 7
27 NC
NC
NC
A4 8
26 NC
NC
NC
A3 9
A2 10
25 VCC VCC
VCC
24 OE# INIT# INIT#
A1 11
23 WE# LFRAME# FWH4
A0 12
22 NC NC
NC
I/O0 13
21 I/O7 RES
14 15 16 17 18 19 20
RES
32-PIN PLCC
FWH
VCC
NC
NC
GND
IC
GPI4
CLK
VCC
NC
RST#
GPI3
GPI2
GPI1
GPI0
WP#
TBL#
LPC
VCC
NC
NC
GND
IC
GPI4
CLK
VCC
NC
RST#
GPI3
GPI2
GPI1
GPI0
WP#
TBL#
A/A Mux
VCC
NC
NC
GND
IC
A10
R/C#
VCC
NC
RST#
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A/A Mux LPC
FWH
32
OE# INIT#
INIT#
31 WE# LFRAME# FWH4
30
NC NC
NC
29
I/O7 RES
RES
28
I/O6 RES
RES
27
I/O5 RES
RES
26
I/O4 RES
RES
25
I/O3 LAD3
FWH3
24
GND GND
GND
23
I/O2 LAD2
FWH2
22
I/O1 LAD1
FWH1
21
I/O0 LAD0
FWH0
20 A0 RES ID0
19 A1 RES ID1
18 A2 RES ID2
17 A3 RES ID3
Programmable Microelectronics Corp.
32-PIN (8mm x 14mm) VSOP
3
Issue Date: December, 2003 Rev: 1.4


3Pages


PM49FL004 電子部品, 半導体
PMC
BLOCK DIAGRAM
TBL#
WP#
INIT#
FWH[3:0] or
LAD[3:0]
FWH4 or LFRAME#
CLK
GPI[4:0]
A[10:0]
I/O[7:0]
WE#
OE#
R/C#
IC
RST#
FWH/LPC
MODE
INTERFACE
PP MODE
INTERFACE
Pm49FL002 / 004
ERASE/PROGRAM
VOLTAGE
GENERATOR
HIGH VOLTAGE
SWITCH
I/O BUFFERS
CONTROL
LOGIC
DATA
LATCH
SENSE
AMP
Y-DECODER
X-DECODER
Y-GATING
MEMORY
ARRAY
DEVICE OPERATION
MODE SELECTION
PRODUCT IDENTIFICATION
The Pm49FL002/004 can operate in two configurable
interfaces: The In-System Hardware interface and Ad-
dress/Address Multiplexed (A/A Mux) interface con-
trolled by IC pin. If the IC pin is set to logic high (VIH),
the devices enter into A/A Mux interface mode. If the IC
pin is set logic low (VIL), the devices will be in in-system
hardware interface mode. During the in-system hard-
ware interface mode, the devices can automatically de-
tect the Firmware Hub (FWH) or Low Pin Count (LPC)
memory cycle sent from host system and response to
the command accordingly. The IC pin must be setup
during power-up or system reset, and stays no change
during device operation.
The product identification mode can be used to read the
Manufacturer ID and the Device ID by a software Prod-
uct ID Entry command in both in-system hardware in-
terface and A/A Mux interface modes. The product
indentification mode is activated by three-bus-cycle com-
mand. Refer to Table 1 for the Manufacturer ID and De-
vice ID of Pm49FL00x and Table 14 for the SDP Com-
mand Definition.
In FWH mode, the product identification can also be
read directly at FFBC0000h for Manufacturer ID - 9Dh
and FFBC0001h for Device ID in the 4 GByte system
memory map.
When working in-system, typically on a PC or Note-
book, the Pm49FL002/004 are connected to the host
system through a 5-pin communication interface oper-
ated based on a 33-MHz synchronous clock. The 5-pin
interface is defined as FWH[3:0] and FWH4 pins under
FWH mode or as LAD[3:0] and LFRAME# pins under
LPC mode for easy understanding as to those existing
compatible products. When working off-system, typi-
cally on a EPROM Programmer, the devices are oper-
ated through 11-pin multiplexed address - A[10:0] and
8-pin data I/O - I/O[7:0] interfaces. The memory ad-
dresses of devices are input through two bus cycles as
row and column addresses controlled by a R/C# pin.
Table 1: Product Identification
Description
Manufacturer ID
Device ID
Pm49FL002
Pm49FL004
Address
00000h
00002h
2Mb
4Mb
00001h
Data
9Dh
7Fh
6Dh
6Eh
Programmable Microelectronics Corp. 6 Issue Date: December, 2003 Rev: 1.4

6 Page



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共有リンク

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部品番号部品説明メーカ
PM49FL002

2 Mbit / 4 Mbit 3.3 Volt-only Fimware Hub / LPC Flash Memory

Programmable Microelectronics
Programmable Microelectronics
PM49FL004

2 Mbit / 4 Mbit 3.3 Volt-only Fimware Hub / LPC Flash Memory

Programmable Microelectronics
Programmable Microelectronics


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