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MN6153UC の電気的特性と機能

MN6153UCのメーカーはPanasonic Semiconductorです、この部品の機能は「PLL LSI with Built-In Prescaler」です。


製品の詳細 ( Datasheet PDF )

部品番号 MN6153UC
部品説明 PLL LSI with Built-In Prescaler
メーカ Panasonic Semiconductor
ロゴ Panasonic Semiconductor ロゴ 




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MN6153UC Datasheet, MN6153UC PDF,ピン配置, 機能
For Communications Equipment
MN6153UC
PLL LSI with Built-In Prescaler
Overview
The MN6153UC is a CMOS LSI for a phase-locked
loop (PLL) frequency synthesizer with serial data input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.0 to 1.4 V) and low power consumption (0.5
mW for VDD=1.03 V, FIN= 60 MHz).
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
Features
Low power supply voltage: VDD=1.0 to 1.4V
Low power consumption: 0.5mW (VDD=V1.03V,
FIN=60MHz)
High-speed operation: FIN=60MHz
(VDD=1.03V)
Frequency dividing ratios in reference frequency
dividing stage: 5 to 131,071
Frequency dividing ratios in comparator stage:
272 to 262,143
Lock detector output pin
Two types of phase comparator output
- Internal charge pump output
- Output for external charge pump
Output monitor pins for both comparator and reference
frequency dividing stages
Pin Assignment
XIN
XOUT
FV
VDD
DOP
VSS
VCP
FIN
1
2
3
4
5
6
7
8
16 OR
15 OV
14 LC
13 FR
12 PS
11 LE
10 DATA
9 CLK
(TOP VIEW)
SSOP016-P-0225

1 Page





MN6153UC pdf, ピン配列
For Communications Equipment
MN6153UC
Pin Descriptions
Pin No. Symbol
1 XIN
2 XOUT
3 FV
4 VDD
5 DOP
6 VSS
7 VCP
8 FIN
9 CLK
10 DATA
11 LE
12 PS
13 FR
14 LC
15 OV
16 OR
Function Description
Crystal oscillator connection pins:
XIN =Oscillator circuit input pin;
XOUT=Oscillator circuit output pin.
Frequency divider output signal in comparator stage.
Phase comparator input monitor.
Power supply
Low-pass filter connection pin. Use a passive filter.
Ground
Power supply pin for built-in charge pump
Frequency divider input pin in comparator stage.
Shift register clock input pin.
The chip latches data at the rising edge of the CLK signal.
Shift register data input pin.
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
Load enable signal input pin.
This is the latch-write-enable signal. It is at "H" level for write.
Power save control signal input pin.
"H" level input starts the frequency divider and places the chip in operational mode.
"L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
Reference frequency divider output signal.
Phase comparator input monitor.
Charge pump control signal output pin.
When frequency divider operation is stopped, this pin is at "L" level,
the internal charge pump output is in the high-impedance state, and the loop is
opened.
Phase comparator output pin for external charge pump.
(OR provides N-channel open drain output.)


3Pages


MN6153UC 電子部品, 半導体
MN6153UC
For Communications Equipment
Absolute Maximum Ratings
Parameter
Power supply voltage
Power supply voltage
Input pin voltage
Output pin voltage
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VDD
VCP
VI
VO
PD
Topr
Tstg
Rating
– 0.3 to +3.0
– 0.3 to +4.0
VSS – 0.3 to VDD +0.3
VSS – 0.3 to VDD +0.3
20
–10 to +60
–55 to +125
Operating Conditions
VSS=0V, Ta=–10 to +60˚C
Parameter
Power supply voltage
Power supply voltage
Symbol
VDD
VCP
Test Conditions
min typ
1.0 1.1
2.5 3.0
Electric Characteristics
VCP=2.5V, Ta=–10 to +60˚C
Parameter
Symbol
Test Conditions
min typ
Power supply pin
Power supply current
VDD VDD=1.03V
IDD FIN=100MHz, XIN=20MHz,
PS="H"
IDstop
PS="L" (at power save operation)
Input Pins CLK, DATA, LE, PS VDD=1.0 to 1.4V
"H" level input voltage
VIH
VDD – 0.2
"L" level input voltage
VIL
VSS
Input leakage current
ILI
Input Pin
Input voltage
Input current
FIN VDD=1.03 to 1.4V
VIN
IIF
Pull-up resistor is present
(PS="L")
0.4
–10
Input leakage current
ILIF
Maximum operating frequency FINMAX
Minimum operating frequency FINMIN
Input Pin XIN VDD=1.0 to 1.4V
Input voltage
VIN
Input current
IIX
VIN=0 or VDD (PS="H")
VIN=0.4 Vp-p
VIN=0.4 Vp-p
Pull-up resistor is present
(PS="L")
60
0.4
– 0.2
Input leakage current
ILIX VIN=0 or VDD
Unit
V
mW
˚C
max Unit
1.4 V
3.2 V
max Unit
0.5 mA
2.0 µA
VDD
V
0.2
±1.0 µA
Vp-p
–100 µA
±20 µA
MHz
10 MHz
Vp-p
–1.5 mA
2.0 µA

6 Page



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部品番号部品説明メーカ
MN6153UC

PLL LSI with Built-In Prescaler

Panasonic Semiconductor
Panasonic Semiconductor


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