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PDF STV5346 Data sheet ( Hoja de datos )
| Número de pieza | STV5346 | |
| Descripción | MONOCHIP TELETEXT DECODER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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STV5346
STV5346/H - STV5346/T
MONOCHIP TELETEXT DECODER
WITH 8 INTEGRATED PAGES
. COMPLETE TELETEXT DECODER INCLUD-
. ING AN 8 PAGE MEMORY ON A SINGLE
CHIP
UPWARD SOFTWARE COMPATIBLE WITH
PREVIOUS SGS-THOMSON’s MULTICHIP
SOLUTIONS (SAA5231, SDA5243, STV5345)
. SINGLE +5V SUPPLY VOLTAGE
. SINGLE 13.875MHz CRYSTAL
. REDUCED SET OF EXTERNAL COMPO-
NENTS, NO EXTERNAL ADJUSTMENT
. OPTIMIZED NUMBER OF DIGITAL SIGNALS
REDUCING EMC RADIATION
. HIGH DENSITY CMOS TECHNOLOGY
. DIGITAL DATA SLICER AND DISPLAY CLOCK
PHASE LOCK LOOP
. 28 PIN DIP & SO PACKAGE
DIP28
(Plastic Package)
ORDER CODE :
STV5346 West European
STV5346/H East European
STV5346/T Turkish & European
SO28
(Plastic Package)
ORDER CODE :
STV5346D West European
STV5346D/H East European
STV5346D/T Turkish & European
PIN CONNECTIONS
DESCRIPTION
The STV5346 decoder is a computer-controlled
teletext device including an 8 page internal mem-
ory. Data slicing and capturing extracts the teletext
information embedded in the composite video sig-
nal. Control is accomplished via a two wire serial
I2C bus . Internal ROM provides a character set
suitable to display text using up to seven national
languages. Different ROM versions will support
several national character sets. Hardware and soft-
ware features allow selectable master/slave syn-
chronization configurations. The STV5346 also
supports facilities for reception and display of cur-
rent level protocol data.
November 1995
CVBS
MA/SL
VDDA
POL
STTV/LFB
FFB
VSSD
R
G
B
RGB REF
BLAN
COR
ODD/EVEN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 CBLK
27 TEST
26 VSSA
25 VSSO
24 XTI
23 XTO
22 VDDD
21 VCR/TV
20 RESERVED
19 RESERVED
18 RESERVED
17 SDA
16 SCL
15 Y
1/21
1 page  
STV5346 - STV5346/H - STV5346/T
Figure 1 : Display Output Timing
LSP
(TCS)
0 4.66
R.G.B.Y
(1)
40µs
64
0 16.67
56.67
(a) LINE RATE all timings in µs
R.G.B.Y
(1)
lines 42 to 291 inclusive
(and 355 to 604 inclusive interlaced)
0 41
(b) FIELD RATE
291 312
line numbers
Figure 2 : Serial Bus Timing
SDA
SCL
t BUF
t LOW
t HD,STA
t R t HD,DAT
tF
t HIGH
t SU,DAT
SDA
VIH = 3V , VIL = 1.5V
t SU,STA
t SU,STO
5/21
5 Page 
STV5346 - STV5346/H - STV5346/T
FUNCTIONAL DESCRIPTION (continued)
III - I2C Bus Register Map (continued)
III.1 - Register Functions
Register
Function
Bit(s)
SEL 11B (D0)
Description
Selection of register 11B (D0 = 1) or 11A (D0 = 0)
R0
Address
00H
R11 adressing and
pin functions control
EVEN OFF (D2)
DISABLE ROLLING
HEADER
FREE RUNNING
PLL (D6)
Control of ODD/EVEN pin : EVEN signal output
(D2 = 0) or grounded (D2 = 1)
D4 = 1, Disable rolling header
D4 = 0, Normal operation
D6 = 0, PLL locks on line frequency
D6 = 1, to force free running mode
X/24 POSITION (D7)
T1 (D1)
0
0
1
1
T0 (D0)
0
1
0
1
D7 = 0, packet X/24 stored to chapter 4 to 7/row 20
D7 = 1, packet X/24 stored to chapter 0 to 3/row 24
Character display line control :
312/313 line MIX - mode with interlace
312/313 line TEXT - mode without interlace
312/312 line Terminal mode without interlace
External synchronization. SCS mode (scan field synchro)
R1
Address
01H
Operating mode
controls
TCS ON (D2)
DEW / FULLFIELD
(D3)
Master Mode (MA/SL Pin 2 = 0)
case POL Pin 4 = 0
D2 = 0, Pin 5 = VCS
D2 = 1, Pin 5 = TCS
Slave Mode (MA/SL Pin 2 = VDD)
No effect
Selection of field flyback mode or full channel mode
(D3 = 1) for recovering of Teletext data.
GHOST ROW
ENABLE (D4)
Selection of ghost row mode (D4 = 1)
ACQUISITION
ON / OFF (D5)
Control of acquisition operation (D5 = 0 enables
acquisition)
7 bits + parity or 8 bits Selection of received data format either 7 bits with parity
without parity (D6) (D6 = 0) or 8 bits without parity (D6 = 1).
R2
Address
02H
Addressing
information for
a page request
SC0, SC1, SC2
(D0, D1, D2)
TB (D3)
A0, A1 (D4, D5)
Address the first column of the on chip page request
RAM to be written.
Test bit equal to ”0” in the normal working mode.
Address a group of four consecutive pages currently
used for data acquisition.
A2 (D6)
Address of one of the two groups of four pages for
acquisition in normal mode.
R3
Address
03H
R4
Address
04H
Data relative to the
requested page
(see Table 3)
Selection of one
of eight pages
to display
PRD0 - PRD4
(D0 - D4)
A0, A1, A2
(D0, D1, D2)
Written data in the page request RAM, starting with the
columns addressed by SC0,SC1,SC2.
These 3 bits correspond to the logical states of the 3
address lines (A10, A11, A12) during memory read cycles.
PON (D0, D1)
Picture on (IN: D0, OUT: D1)
R5
Address
05H
Display control for
normal operation
TEXT (D2, D3)
COR (D4, D5)
BKGND (D6, D7)
IN / OUT
Text on (IN: D2, OUT: D3)
Contrast reduction on (IN: D4, OUT: D5)
Background color on (IN: D6, OUT: D7)
Enable inside/outside the box
R6
Address
06H
Display control for
news-flash subtitle
generation
See R5
See R5
11/21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet STV5346.PDF ] | |
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