PDF CY7C1372CV25 Data sheet ( Hoja de datos )

Número de pieza	CY7C1372CV25
Descripción	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
Fabricantes	Cypress
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CY7C1370CV25 CY7C1372CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 225, 200 and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • Single 2.5V power supply • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.8 ns (for 225-MHz device) — 3.0 ns (for 200-MHz device) — 3.4 ns (for 167-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • Available in 100 TQFP, 119 BGA, and 165 fBGA packages • IEEE 1149.1 JTAG Boundary Scan • Burst capability—linear or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370CV25 and CY7C1372CV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370CV25 and CY7C1372CV25 are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWa–BWd for CY7C1370CV25 and BWa–BWb for CY7C1372CV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Logic Block Diagram–CY7C1370CV25 (512K x 36) A0, A1, A MODE CLK C CEN ADV/LD BWa BWb BWc BWd WE ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 A1 D1 Q1 A1' A0 D0 BURST Q0 A0' LOGIC ADV/LD C WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S E D A T A S T E E R I N O U T P U T B U F F E R S E G INPUT REGISTER 1 E INPUT REGISTER 0 E DQs DQPa DQPb DQPc DQPd OE CE1 READ LOGIC CE2 CE3 ZZ SLEEP CONTROL Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05235 Rev. C Revised June 03, 2004 1 page CY7C1370CV25 CY7C1372CV25 Pin Configurations (continued) 165-Ball fBGA Pinout CY7C1370CV25 (512K × 36) – 13 × 15 fBGA 1234 5678 A E(288) A CE1 BWc B NC A CE2 BWd C DQPc NC VDDQ VSS D DQc DQc VDDQ VDD E DQc DQc VDDQ VDD F DQc DQc VDDQ VDD G DQc DQc VDDQ VDD H NC NC / VDD NC VDD J DQd DQd VDDQ VDD K DQd DQd VDDQ VDD L DQd DQd VDDQ VDD M DQd DQd VDDQ VDD N DQPd NC VDDQ VSS P NC E(72) A A BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 CEN WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO ADV/LD OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A R MODE E(36) A A TMS A0 TCK A CY7C1372CV25 (1M × 18) – 13 × 15 fBGA 1234 A E(288) B NC A A CE1 BWb CE2 NC C NC NC VDDQ VSS D NC DQb VDDQ VDD E NC DQb VDDQ VDD F NC DQb VDDQ VDD G NC DQb VDDQ VDD H NC NC / VDD NC VDD J DQb NC VDDQ VDD K DQb NC VDDQ VDD L DQb NC VDDQ VDD M DQb NC VDDQ VDD N DQPb NC VDDQ VSS P NC E(72) A A 5 NC BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI 6 CE3 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1 7 CEN WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO 8 ADV/LD OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A R MODE E(36) A A TMS A0 TCK A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 A NC A E(144) NC DQPb DQb DQb DQb DQb DQb DQb DQb DQb NC ZZ DQa DQa DQa DQa DQa DQa DQa DQa NC DQPa A NC AA 10 11 AA A E(144) NC DQPa NC DQa NC DQa NC DQa NC DQa NC ZZ DQa NC DQa NC DQa NC DQa NC NC NC A NC AA Document #: 38-05235 Rev. C Page 5 of 27 5 Page CY7C1370CV25 CY7C1372CV25 When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 38-05235 Rev. *C Page 11 of 27 11 Page

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