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11C06 の電気的特性と機能

11C06のメーカーはNationalです、この部品の機能は「750 MHz D-Type Flip-Flop」です。


製品の詳細 ( Datasheet PDF )

部品番号 11C06
部品説明 750 MHz D-Type Flip-Flop
メーカ National
ロゴ National ロゴ 




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11C06 Datasheet, 11C06 PDF,ピン配置, 機能
Not Intended For New Designs
August 1992
11C06
750 MHz D-Type Flip-Flop
General Description
The 11C06 is a high-speed ECL D-Type Master-Slave Flip-
Flop capable of toggle rates over 750 MHz Designed pri-
marily for high-speed prescaling it can also be used in any
application which does not require preset inputs The circuit
is voltage-compensated which makes input thresholds and
output levels insensitive to VEE variations Complementary
Q and Q outputs are provided as are two Data inputs Clock
and Clock Enable inputs The 11C06 is pin-compatible with
the Motorola MC1690L but is a higher-frequency replace-
ment
Logic Symbol
Connection Diagrams
16-Pin DIP
16-Pin Flatpak
Pin Names
Dn
CP
CE
QQ
TL F 9890–3
Description
Data Input
Clock Input
Clock Enable (Active LOW)
Outputs
TL F 9890 – 1
Truth Table
CE CP
LL
LH
LL
LL
HX
H e HIGH Voltage Level
L e LOW Voltage Level
X e Don’t Care
L e LOW to HIGH Transition
Qnb1 e Previous State
D
X
X
L
H
X
TL F 9890 – 2
Qn
Qnb1
Qnb1
L
H
Qnb1
C1995 National Semiconductor Corporation TL F 9890
RRD-B30M115 Printed in U S A

1 Page





11C06 pdf, ピン配列
Functional Description
While the clock is LOW the slave is held steady and the
information on the D input is permitted to enter the master
The next transition from LOW to HIGH locks the master in
its present state making it insensitive to the D input This
transition simultaneously connects the slave to the master
causing the new information to appear on the outputs Mas-
ter and slave clock thresholds are internally offset in oppo-
site directions to avoid race conditions or simultaneous
master-slave changes when the clock has slow rise or fall
times
The CP and CE inputs are logically identical but physical
constraints associated with the Dual-In-Line package make
the CE input slower at the upper end of the toggle range To
prevent new data from entering the master on the next CP
LOW cycle CE should go HIGH while CP is still HIGH
RT e 50X termination of scope
L1 e 50X impedance lines
All input transition times are 2 0 ns g0 2 ns
FIGURE 1 Propagation Delay (CP to Q)
TL F 9890 – 4
RT e 50X termination of scope
L1 e 50X impedance lines
Adjust VBIAS for a0 7V baseline of
800 mV peak-to-peak sinewave input
All input transition times are 2 0 ns g0 2 ns
FIGURE 2 Toggle Frequency Test Circuit
3
TL F 9890 – 5


3Pages


11C06 電子部品, 半導体
Physical Dimensions inches (millimeters) (Continued)
16 Lead Ceramic Flatpak (F)
NS Package Number W16A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or
systems which (a) are intended for surgical implant
into the body or (b) support or sustain life and whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling can
be reasonably expected to result in a significant injury
to the user
2 A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system or to affect its safety or
effectiveness
National Semiconductor
Corporation
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Arlington TX 76017
Tel 1(800) 272-9959
Fax 1(800) 737-7018
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Fax (852) 2736-9960
National Semiconductor
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Tel 81-043-299-2309
Fax 81-043-299-2408
National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

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共有リンク

Link :


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