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PDF MC74HCT574A Data sheet ( Hoja de datos )
| Número de pieza | MC74HCT574A | |
| Descripción | Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74HCT574A
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT574A is identical in pinout to the LS574. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The Output Enable input does not affect the states
of the flip–flops, but when Output Enable is high, all device outputs
are forced to the high–impedance state. Thus, data may be stored even
when the outputs are not enabled.
The HCT574A is identical in function to the HCT374A but has the
flip–flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
• Output Drive Capability: 15 LSTTL Loads
• TTL NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 286 FETs or 71.5 Equivalent Gates
http://onsemi.com
20
1
20
1
PDIP–20
N SUFFIX
CASE 738
MARKING
DIAGRAMS
20
MC74HCT574AN
AWLYYWW
SOIC WIDE–20
DW SUFFIX
CASE 751D
1
20
HCT574A
AWLYYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package Shipping
MC74HCT574AN
PDIP–20 1440 / Box
MC74HCT574ADW SOIC–WIDE 38 / Rail
MC74HCT574ADWR2 SOIC–WIDE 1000 / Reel
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 8
1
Publication Order Number:
MC74HCT574A/D
1 page  
MC74HCT574A
EXPANDED LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
2345 6789
CLOCK 11
ENABLE 1
OUTPUT
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
19 18 17 16
15 14 13 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
tr tf
CLOCK
Q
2.7 V
1.3 V
0.3 V
tw
90%
1.3 V
10%
1/fmax
tPLH
tPHL
tTLH tTHL
Figure 1.
DATA
CLOCK
VALID
1.3 V
tsu th
1.3 V
Figure 3.
SWITCHING WAVEFORMS
3.0 V
GND
3.0 V
GND
3.0 V
GND
OUTPUT
ENABLE
Q
Q
1.3 V
tPZL tPLZ
1.3 V
tPZH tPHZ
1.3 V
10%
90%
Figure 2.
TEST POINT
3.0 V
GND
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
OUTPUT
CL*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 5. Test Circuit
http://onsemi.com
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC74HCT574A.PDF ] | |
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