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MT5C1001 の電気的特性と機能

MT5C1001のメーカーはASIです、この部品の機能は「SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 MT5C1001
部品説明 SRAM
メーカ ASI
ロゴ ASI ロゴ 




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MT5C1001 Datasheet, MT5C1001 PDF,ピン配置, 機能
Austin Semiconductor, Inc.
SRAM
MT5C1001
Limited Availability
1M x 1 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-92316
• MIL-STD-883
FEATURES
• High Speed: 20, 25, 35, and 45
• Battery Backup: 2V data retention
• Low power standby
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
• Three-state output
OPTIONS
• Timing
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-20
-25
-35
-45
-55*
-70*
• Package(s)
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
C No. 109
EC No. 207
F No. 303
DCJ No. 501
• Operating Temperature Ranges
Industrial (-40oC to +85oC)
IT
Military (-55oC to +125oC)
XT
• 2V data retention/low power L
*Electrical characteristics identical to those provided for the
45ns access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
PIN ASSIGNMENT
(Top View)
28-Pin DIP (C)
(400 MIL)
A10 1
A11 2
A12 3
A13 4
A14 5
A15 6
NC 7
A16 8
A17 9
A18 10
A19 11
Q 12
WE\ 13
Vss 14
28 Vcc
27 A9
26 A8
25 A7
24 A6
23 A5
22 A4
21 NC
20 A3
19 A2
18 A1
17 A0
16 D
15 CE\
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
A10 1
A11 2
A12 3
NC 4
A13 5
A14 6
A15 7
NC 8
A16 9
A17 10
A18 11
A19 12
NC 13
Q 14
WE\ 15
Vss 16
32 Vcc
31 NC
30 A9
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 NC
22 A2
21 NC
20 A1
19 A0
18 D
17 CE\
32-Pin Flat Pack (F)
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3 2 Vcc
3 1 NC
3 0 A9
2 9 A8
2 8 A7
2 7 A6
2 6 A5
2 5 A4
2 4 A3
2 3 NC
2 2 A2
2 1 NC
2 0 A1
1 9 A0
18 D
1 7 CE\
GENERAL DESCRIPTION
The MT5C1001 employs low power, high-performance
silicon-gate CMOS technology. Static design eliminates the
need for external clocks or timing strobes while CMOS circuitry
reduces power consumption and provides for greater
reliability.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE|) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (ISBC2) over the standard
version.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1

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MT5C1001 pdf, ピン配列
Austin Semiconductor, Inc.
SRAM
MT5C1001
Limited Availability
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Input Relative to Vss................................-.5V to +7V
Voltage on Vcc Supply Relative to Vss...............................-.5V to +7V
Voltage Applied to Q............................................................-.5V to +6V
Storage Temperature......................................................-65oC to +150oC
Power Dissipation..............................................................................1W
Short Circuit Output Current.........................................................20mA
Lead Temperature (soldering 10 seconds)....................................+260oC
Junction Temperature..................................................................+175oC
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC; VCC = 5V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
CONDITIONS
0V VIN VCC
Output(s) disabled
0V < VOUT < VCC
IOH = -4.0mA
IOL = 8.0mA
SYMBOL
VIH
VIL
ILI
ILO
VOH
VOL
MIN
2.2
-0.5
-5
-5
2.4
MAX
VCC+0.5
0.8
5
UNITS
V
V
µA
5 µA
V
0.4 V
NOTES
1
1, 2
1
1
PARAMETER
Power Supply
Current: Operating
Power Supply
Current: Standby
CONDITIONS
CE\ < VIL; VCC = MAX
f = MAX = 1/tRC (MIN)
Output Open
CE\ > VIH; VCC = MAX
f = MAX = 1/tRC (MIN)
Output Open
CE\ > VIH; All Other Inputs
< VIH or > VIH, VCC = MAX
f = 0 Hz
CE\ > VCC -0.2V; VCC = MAX
VIL < VSS +0.2V
VIH > VCC -0.2V; f = 0 Hz
"L" Version Only
SYM -20
MAX
-25 -35
-45 UNITS NOTES
Icc 125 120 115 110 mA
3
ISBT1 50 45 40 35 mA
ISBT2 25 25 25 25 mA
ISBC2 10 10 10 10 mA
ISBC2 5 5 5 5 mA
CAPACITANCE
PARAMETER
Input Capacitance (A3-A5, A15 -A17)
Output Capactiance (Q)
Input Capacitance: (All Other Inputs)
MT5C1001
Rev. 2.0 2/00
CONDITIONS
TA = 25oC, f = 1MHz
VCC = 5V
SYMBOL
CI
Co
CI
MAXIMUM
10
8
8
UNITS
pF
pF
pF
NOTES
4
4
4
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3


3Pages


MT5C1001 電子部品, 半導体
Austin Semiconductor, Inc.
SRAM
MT5C1001
Limited Availability
ADDRESS
DQ
READ CYCLE NO. 1 8, 9
ttOHH
PREVIOUS DATA VALID
ttAAAA
ttRRCC
VALID
DATA VALID
READ CYCLE NO. 2 7, 8, 10
ttRRCC
CE\
ttLLZZCCE EtAtACCE E
ttHHZZCCEE
DQ DATA VALID
ttPPUU
Icc
ttPPDD
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6

6 Page



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共有リンク

Link :


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