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PDF ST9291 Data sheet ( Hoja de datos )
| Número de pieza | ST9291 | |
| Descripción | 16-48K ROM HCMOS MCU WITH ON SCREEN DISPLAY AND VOLTAGE TUNINGOUTPUT | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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® ST9291
16-48K ROM HCMOS MCU WITH
ON SCREEN DISPLAY AND VOLTAGE TUNING OUTPUT
FUNCTIONAL DESCRIPTION
Register oriented 8/16 bit CORE with
RUN, WFI and HALT modes
Minimum instruction cycle time: 500ns
(12MHz internal)
16 to 48K bytes of ROM,
384/640 bytes of RAM,
224 general purpose registers available as RAM,
accumulators or index registers (Register File)
42-lead Shrink DIP package or
56-lead Shrink DIP package
Interrupt handler and Serial Peripheral Interface
as standard features
31 (42 pin package) / 42 (56 pin package) fully
programmable I/O pins
34 character x15 rows software programmable
On Screen Display module with colour, italic, un-
derline, flash, transparent and fringe attribute
options
14-bit Voltage Synthesis for tuning reference
voltage.
8 8-bit PWM D/A outputs with repetition frequency
2 to 32kHz and 12V Open Drain Capability
16 bit Timer with 8 bit Prescaler, able to be used
as a Watchdog Timer
16-bit programmable Slice Timer with 8-bit pres-
caler
3 channel Analog to Digital Converter, with inte-
gral sample and hold, fast 5.75µs conversion
time, 6-bit guaranteed resolution
Rich Instruction Set and 14 Addressing modes
Division-by-Zero trap generation
Versatile Development tools, including assembler,
linker, C-compiler, archiver, graphic oriented de-
bugger and hardware emulators
Real Time Operating System
Windowed EPROM parts available for prototyp-
ing and pre-production development phases
PSDIP42
PSDIP56
(Ordering Information at the end of the Datasheet)
DEVICE SUMMARY
Device
ST9291J2/N2
ST9291J3/N3
ST9291J4/N4
ST9291J5/N5
ST9291J6/N6
ST9291J7/N7
ROM
16K
16K
24K
24K
32K
48K
RAM
384
640
384
640
640
640
PACKAGE
PSDIP42/56
PSDIP42/56
PSDIP42/56
PSDIP42/56
PSDIP42/56
PSDIP42/56
July 1995
1/20
1 page  
ST9291
PIN DESCRIPTION (Continued)
Table 1.ST9291 I/O Port Alternative Function Summary
I/O PORT
Port.bit
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.1
P2.2
P2.2
P2.3
P2.3
P2.4
P2.5
P2.5
P3.0
P3.1
P3.2
P3.3
Name
INT7
INT5
AIN1
INT0
AIN2
INT6
VSO1
NMI
AIN3
VSO2
FB
R
G
B
Func tion
Alternate Function
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I External Interrupt 7 with Schmitt Trigger
I External Interrupt 5 with Schmitt Trigger
I A/D Analog Input 1
I External Interrupt 0
I A/D Analog Input 2
I External Interrupt 6
O Voltage Synthesis Output 1
I Non-Maskable Interrupt
I A/D Analog Input 3
O Voltage Synthesis Output 2
O Fast Blanking OSD output
O Red Video Colour OSD output
O Green Video Colour OSD output
O Blue Video Colour OSD output
Pin Assignment
9291J
9291N
10 12
9 11
8 10
79
68
56
45
34
- 52
- 51
- 50
- 49
- 48
- 47
- 46
- 45
12
42 1
42 1
41 56
41 56
40 55
40 55
39 54
38 53
38 53
18 23
17 22
16 21
15 20
5/20
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5 Page 
ST9291
1.1.3 SYSTEM REGISTERS
Following is the description of System Registers.
For PORT0 to PORT5 Registers, please refer to
I/O Port Chapter.
Figure 1-8. System Register
R239 (EFh)
R238 (EEh)
R237 (EDh)
R236 (ECh)
R235 (EBh)
R234 (EAh)
R233 (E9h)
R232 (E8h)
R231 (E7h)
R230 (E6h)
R229 (E5h)
R228 (E4h)
R227 (E3h)
R226 (E2h)
R225 (E1h)
R224 (E0h)
SYS. STACK POINTER LOW
SYS. STACK POINTER HIGH
USER STACK POINTER LOW
USER STACK POINTER HIGH
MODE REGISTER
PAGE POINTER
REGISTER POINTER 1
REGISTER POINTER 0
FLAGS
CENTRAL INT. CNTL REG
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
1.1.3.1 Central Interrupt Control Register
This Register CICR is located in the system Regis-
ter Group at the address R230 (E6h). Please refer
to “INTERRUPT” and “DMA” chapters in order to
get the background of the ST9 interrupt philoso-
phy.
CICR R230 (E6h) System Read/Write
Central Interrupt Control Register
Reset Value : 1000 0111
70
GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0
b7 = GCEN: Global Counter Enable. This bit is the
Global Counter Enable of the Multifunction Timers.
The GCEN bit is ANDed with the CE (Counter En-
able) bit of the Timer Control Register (explained in
the Timer chapter) in order to enable the Timers
when both bits are set. This bit is set after the Re-
set cycle.
b6 = TLIP: Top Level Interrupt Pending. This bit is
automatically set when a Top Level Interrupt Re-
quest is recognized. This bit can also be set by
Software in order to simulate a Top Level Interrupt
Request.
b5 = TLI: Top Level Interrrupt bit. When this bit is
set, a Top Level interrupt request is acknowledged
depending on the IEN bit and the TLNM bit (in
Nested Interrupt Control Register). If the TLM bit is
reset the top level interrupt acknowledgement de-
pends on the TLNM alone.
b4 = IEN: Enable Interrupt. This bit, (when set), al-
lows interrupts to be accepted. When reset no in-
terrupts other than the NMI can be acknowledged.
It is cleared by interrupt acknowledgement for con-
current mode and set by interrupt return (iret). It
can be managed by hardware and software (ei
and di instruction).
b3 = IAM: Interrupt Arbitration Mode. This bit cov-
ers the selection of the two arbitration modes, the
Concurrent Mode being indicated by the value “0”
and the Fully Automatic Nested Mode by the value
“1”. This bit is under software control.
b2-b0 = CPL2-CPL0: Current Priority Level. These
three bits record the priority level of the interrupt
presently under service (i.e. the Current Priority
Level, CPL). For these priority levels 000 is the
highest priority and 111 is the lowest priority. The
CPL bits can be set by hardware or software and
give the reference by which following interrupts are
either left pending or able to interrupt the current
interrupt. When the present interrupt is replaced by
one of a greater priority, the current priority value is
automatically stored until required.
11/20
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