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PDF MC68B00 Data sheet ( Hoja de datos )

Número de pieza MC68B00
Descripción 8-BIT MICROPROCESSING UNIT
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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Advance Inforlll.ation
1.5 AND 2.0 MHz COMPONENTS
FOR THE M6800 MICROCOMPUTER SYSTEM
The eight devices described in this data sheet extend the operating
frequency of the M6800 Microcomputer Family. The block diagrams
and device operation are the same as for the basic M6800-series
components.
• Fully Hardware and Software Compatible with the
M6800 Family
• Power Dissipation Approximately 20% Lower Than on
Standard MC6800 Series
• Clock Specification Improved for Reduced Complexity of
Clock Generator/Driver Circuitry
• The MC6821 and its higher-frequency versions provide drive
capability of two TTL loads on all A- and B-side buffers,
improving the drive capability of the MC6820.
1.5 MHz
2.0 MHz
MC68AOO·MC68BOO
MPH
MC68A21· MC68B21
PIA
MC68A50·MC68B50
ACIA
MCM68AIO· MCM68BIO
RAM
MOS
(N-eHANNEL, SILICON-GATE)
MICROPROCESSOR SYSTEM
COMPONENTS
M6800 MICROCOMPUTER FAMILY
BLOCK DIAGRAM
MC68AOO
Microprocessor
MC68BOO
P SUFFIX
PLASTIC PACKAGE
CASE 711
NOT SHOWN: L SUFFIX
CERAMIC PACKAGE
CASE 715
Address
Bus
This is advance information and specifications are subject to change without notice.
For additional information on these devices-
including block diagrams, signal descriptions, device
operation and pin assignments-refer to the M6800
Microcomputer System Design Data brochure.
©MOTOROLA INC., 1977
ADI-429

1 page




MC68B00 pdf
TIMING CHARACTERISTICS (Vcc = 5.0 V ±5%, VSS = 0, T A = 0 to 700 C unless otherwise noted.)
Characteristic
Peripheral Data Setup Time
Peripheral Data Hold Time
Delay Time, Enable negative transition to CA2 negative transition
Delay Time, Enable negative transistion to CA2 positive transition
Rise and Fall Times for CA 1 and CA2 input signals
Delay Time from CA 1 active transition to CA2 positive transition
Delay Time, Enable negative transition to Peripheral Data Valid
Delay Time, Enable negative transition to Peripheral CMOS Data Valid
(VCC - 30%, VCC; Figure 6, Load C)
PAO-PA7, CA2
Delay Time, Enable positive transition to CB2 negative transition
Delay Time, Peripheral Data Valid to CB2 negative transition
Delay Time, Enable positive transition to CB2 positive transition
Peripheral Control Output Pulse Width, CA2/CB2
Rise and Fall Time for CB1 and CB2 input signals
Delay Time, CB1 active transition to CB2 positive transition
Interrupt Release Time, IROA and IROB
Interrupt Resporlse Time
Interrupt Input Pulse Width
Reset Low Time*
Symbol
tpDSU
tPDH
tCA2
tRS1
t r, tf
tRS2
tpDW
tCMOS
tCB2
tDC
tRS1
PWCT
t r, tf
tRS2
tlR
tRS3
PWI
tRL
MC68A21
Min Max
135 -
0-
- 0.670
- 0.670
- 1.0
- 1.35
- 0.670
- 1.35
-
20
-
550
-
-
-
-
500
0.66
0.670
-
0.670
-
1.0
1.35
1.1
1.0
-
-
*The Reset line must be high a minimum of 1.0 j.lS before addressing the PIA.
MC68B21
Min Max
100 -
0-
- 0.5
- 0.5
- 1.0
- 1.0
- 0.5
- 1.0
- 0.5
20 -
- 0.5
550 -
- 1.0
- 1.0
- 0.85
- 1.0
500 -
0.5 -
Unit
ns
ns
j.lS
j.lS
j.lS
j.lS
j.lS
j.lS
j.lS
ns
j.lS
ns
j.lS
j.lS
j.lS
j.lS
ns
j.lS
BUS TIMING CHARACTERISTICS (VCC = 5.0 V ±5%, VSS = 0, T A = 0 to 700 C unless otherwise noted.)
READ
MC68A21
Characteristic
Symbol Min Max
Enable Cycle Time
Enable Pulse Width, High
Enable Pulse Width, Low
Setup Time, Address and R/W Valid to Enable positive transition
Data Delay Time
Data Hold Time
Address Hold Time
Rise and Fall Time for Enable input
WRITE
tcycE
PWEH
PWEL
~
tAS
tDDR
tH
tAH
t Er, t Ef
0.666
0.280
0.280
140
-
10
10
-
-
-
-
-
220
-
-
25
Enable Cycle Time
Enable Pulse Width, High
Enable Pulse Width, Low
Setup Time, Address and R/W Valid to Enable positive transition
Data Setup Time
Data Hold Time
Address Hold Time
Rise and Fall Time for Enable input
tcycE
PWEH
PWEL
tAS
tDSW
tH
tAH
tEr, t Ef
0.666
0.280
0.280
140
80
10
10
-
-
-
-
-
-
-
-
25
MC68B21
Min Max
0.50
-
0.22
-
0.21
-
70 -
- 180
10 -
10 -
- 25
0.50
0.22
0.21
70
60
10
10
-
-
-
-
-
-
-
-
25
Unit
j.lS
j.lS
j.lS
ns
ns
ns
ns
ns
j.lS
j.lS
j.lS
ns
ns
ns
ns
ns
®1....- MOTOROLA Setniconduc'for Produc'fs Inc.

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