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Número de pieza | IS42S16128 | |
Descripción | 128K words x 16 Bits x 2 Banks SDRAM | |
Fabricantes | Integrated Silicon | |
Logotipo | ||
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No Preview Available ! IS42S16128
ISSI®
128K Words x 16 Bits x 2 Banks (4-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEBRUARY 2000
FEATURES
• Clock frequency: 125 MHz, 100 MHz, 83 MHz
• Two banks can be operated simultaneously and
independently
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto refresh, self refresh
• 1K refresh cycles every 16 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Byte controlled by LDQM and UDQM
• Package 400-mil 50-pin TSOP II
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
DESCRIPTION
ISSI's 4Mb Synchronous DRAM IS42S16128 is organized as
a 131072-word x 16-bit x 2-bank for improved performance.
The synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals refer
to the rising edge of the clock input.
PIN DESCRIPTIONS
A0-A9
A0-A8
A9
A0-A7
I/O0 to I/O15
CLK
CKE
CS
RAS
CAS
WE
LDQM
UDQM
Address Input
Row Address Input
Bank Select Address
Column Address Input
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
VCC
I/O0
I/O1
GNDQ
I/O2
I/O3
VCCQ
I/O4
I/O5
GNDQ
I/O6
I/O7
VCCQ
LDQM
WE
CAS
RAS
CS
A9
A8
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 GND
49 I/O15
48 I/O14
47 GNDQ
46 I/O13
45 I/O12
44 VCCQ
43 I/O11
42 I/O10
41 GNDQ
40 I/O9
39 I/O8
38 VCCQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 NC
31 NC
30 A7
29 A6
28 A5
27 A4
26 GND
Vcc
GND
VccQ
GNDQ
NC
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
ORDERING INFORMATION
Commercial Range: 0⋅C to 70⋅C
Frequency
125 MHz
100 MHz
83 MHz
Speed (ns)
8
10
12
Order Part No.
IS42S16128-8T
IS42S16128-10T
IS42S16128-12T
Package
400-mil TSOP II
400-mil TSOP II
400-mil TSOP II
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
1
1 page IS42S16128
ISSI ®
DC ELECTRICAL CHARACTERISTICS
(Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min. Max. Unit
IIL Input Leakage Current
IOL Output Leakage Current
VOH Output High Voltage Level
VOL Output Low Voltage Level
0V ≤ VIN ≤ VCC, with pins other than
the tested pin at 0V
Output is disabled
0V ≤ VOUT ≤ VCC
IOUT = –2 mA
IOUT = +2 mA
–10 10
–10 10
2.4 —
— 0.4
µA
µA
V
V
ICC1
Operating Current(1,2)
One Bank Operation, Burst Length=1
tRC ≥ tRC (min.), IOUT = 0mA
— 100 mA
ICC2P Precharge Standby Current
ICC2PS (In Power-Down Mode)
CKE ≤ VIL (MAX) tCK = tCK (MIN)
tCK = ×
——
——
3 mA
2 mA
ICC2N Precharge Standby Current
ICC2NS (In Non Power-Down Mode)
CKE ≥ VIH (MIN)
tCK = tCK (MIN)
tCK = ×
— — 30 mA
— — 15 mA
ICC3P Active Standby Current
ICC3PS (In Power-Down Mode)
CKE ≤ VIL (MAX)
tCK = tCK (MIN)
tCK = ×
——
——
3 mA
2 mA
ICC3N Active Standby Current
CKE ≥ VIH (MIN) tCK = tCK (MIN)
— — 30 mA
ICC3NS (In Non Power-Down Mode)
tCK = ×
— — 15 mA
ICC4 Operating Current
tCK = tCK (MIN)
CAS latency = 3
-8
— 160 mA
(In Burst Mode)(1)
IOUT = 0mA
-10 — 160 mA
-12 — 120 mA
CAS latency = 2 -8 — 120 mA
-10 — 120 mA
-12 — 110 mA
ICC5 Auto-Refresh Current
tRC = tRC (MIN)
-8 — 100 mA
-10 — 100 mA
-12 —
80 mA
ICC6 Self-Refresh Current
CKE ≤ 0.2V
——
2 mA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time increases.
Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vcc and GND for each memory chip to suppress
power supply voltage noise (voltage drops) due to these transient currents.
2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
5
5 Page IS42S16128
ISSI ®
Self-Refresh Command
(CS, RAS, CAS, CKE = LOW, WE = HIGH)
This command executes the self-refresh operation. The
row address to be refreshed, the bank, and the refresh
interval are generated automatically internally during this
operation. The self-refresh operation is started by drop-
ping the CKE pin from HIGH to LOW. The self-refresh
operation continues as long as the CKE pin remains LOW
and there is no need for external control of any other pins.
The self-refresh operation is terminated by raising the
CKE pin from LOW to HIGH. The next command cannot
be executed until the device internal recovery period (tRC)
has elapsed. After the self-refresh, since it is impossible
to determine the address of the last row to be refreshed,
an auto-refresh should immediately be performed for all
addresses (1024 cycles).
Both banks must be placed in the idle state before
executing this command.
Burst Stop Command
(CS, WE, = LOW, RAS, CAS = HIGH)
The command forcibly terminates burst read and write
operations. When this command is executed during a
burst read operation, data output stops after the CAS
latency period has elapsed.
No Operation
(CS, = LOW, RAS, CAS, WE = HIGH)
This command has no effect on the device.
Device Deselect Command
(CS = HIGH)
This command does not select the device for an object of
operation. In other words, it performs no operation with
respect to the device.
Power-Down Command
(CKE = LOW)
When both banks are in the idle (inactive) state, or when
at least one of the banks is not in the idle (inactive) state,
this command can be used to suppress device power
dissipation by reducing device internal operations to the
absolute minimum. Power-down mode is started by drop-
ping the CKE pin from HIGH to LOW. Power-down mode
continues as long as the CKE pin is held low.
Power-Down Command (cont.)
All pins other than the CKE pin are invalid and none of the
other commands can be executed in this mode. The
power-down operation is terminated by raising the CKE
pin from LOW to HIGH. The next command cannot be
executed until the recovery period (tCKA) has elapsed.
Since this command differs from the self-refresh com-
mand described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tREF). Thus
the maximum time that power-down mode can be held is
just under the refresh cycle time.
Clock Suspend
(CKE = LOW)
This command can be used to stop the device internal
clock temporarily during a read or write cycle. Clock
suspend mode is started by dropping the CKE pin from
HIGH to LOW. Clock suspend mode continues as long as
the CKE pin is held LOW. All input pins other than the CKE
pin are invalid and none of the other commands can be
executed in this mode. Also note that the device internal
state is maintained. Clock suspend mode is terminated by
raising the CKE pin from LOW to HIGH, at which point
device operation restarts. The next command cannot be
executed until the recovery period (tCKA) has elapsed.
Since this command differs from the self-refresh com-
mand described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tREF). Thus
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet IS42S16128.PDF ] |
Número de pieza | Descripción | Fabricantes |
IS42S16128 | 128K words x 16 Bits x 2 Banks SDRAM | Integrated Silicon |
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