PDF ISPLSI1048C-70LQ Data sheet ( Hoja de datos )

Número de pieza	ISPLSI1048C-70LQ
Descripción	In-System Programmable High Density PLD
Fabricantes	Lattice
Logotipo
Hay una vista previa y un enlace de descarga de ISPLSI1048C-70LQ (archivo pdf) en la parte inferior de esta página. Total 14 Páginas
No Preview Available ! ispLSI® 1048C In-System Programmable High Density PLD Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Security Cell Prevents Unauthorized Copying • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 70 MHz Maximum Operating Frequency — fmax = 50 MHz for Industrial and Military/883 Devices — tpd = 16 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology — 100% Tested at Time of Manufacture • IN-SYSTEM PROGRAMMABLE — In-System Programmable™ (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-to- Market, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging • COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEX- IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 A0 A1 A2 A3 Global Routing Pool (GRP) A4 A5 A6 A7 DQ DQ Logic Array D Q GLB DQ D7 D6 D5 D4 D3 D2 D1 D0 B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool C0 C1 C2 C3 C4 C5 C6 C7 CLK Output Routing Pool 0139G1A-isp Description The ispLSI 1048C is a High-Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, two Global Output Enables (GOE), four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048C features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, and the interconnect to provide truly reconfigurable sys- tems. Compared to the ispLSI 1048, the ispLSI 1048C offers two additional dedicated inputs and two new Glo- bal Output Enable pins. The basic unit of logic on the ispLSI 1048C device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. F7 in figure 1. There are a total of 48 GLBs in the ispLSI 1048C devices. Each GLB has 18 inputs, a program- mable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com August 2000 1048C_08 1 1 page Specifications ispLSI 1048C External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 4 COND. #2 DESCRIPTION1 tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3 A 1 Data Propagation Delay, 4PT bypass, ORP bypass A 2 Data Propagation Delay A 3 Clock Frequency with Internal Feedback3 – 4 Clock Frequency with External Feedback ( tsu2 1 + tco1 ) – 5 Clock Frequency, Max Toggle ( 1 twh + tw1 ) – 6 GLB Reg. Setup Time before Clock, 4PT bypass A 7 GLB Reg. Clock to Output Delay, ORP bypass – 8 GLB Reg. Hold Time after Clock, 4 PT bypass – 9 GLB Reg. Setup Time before Clock – 10 GLB Reg. Clock to Output Delay – 11 GLB Reg. Hold Time after Clock A 12 Ext. Reset Pin to Output Delay – 13 Ext. Reset Pulse Duration B 14 Input to Output Enable C 15 Input to Output Disable B 16 Global OE Output Enable C 17 Global OE Output Disable – 20 Ext. Sync. Clock Pulse Duration, High – 21 Ext. Sync. Clock Pulse Duration, Low – 22 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) – 23 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) -70 -50 UNITS MIN. MAX. MIN. MAX. – 16.0 – 22.0 ns – 19.0 – 26.0 ns 70.4 – 50.3 – MHz 47.6 – 34.5 – MHz 83.3 – 58.8 – MHz 9.5 – 13.0 – ns – 10.0 – 14.0 ns 0 – 0 – ns 11.0 – 15.0 – ns – 11.5 – 16.0 ns 0 – 0 – ns – 15.0 – 20.5 ns 10.0 – 13.5 – ns – 20.0 – 27.5 ns – 20.0 – 27.5 ns – 15.0 – 20.5 ns – 15.0 – 20.5 ns 6.0 – 8.5 – ns 6.0 – 8.5 – ns 2.0 – 3.0 – ns 6.5 – 9.0 – ns 1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2- 0030-48C/70, 50 5 5 Page Specifications ispLSI 1048C Pin Description NAME CPGA PIN NUMBERS DESCRIPTION I/O 0 - I/O 5 I/O 6 - I/O 11 I/O 12 - I/O 17 I/O 18 - I/O 23 I/O 24 - I/O 29 I/O 30 - I/O 35 I/O 36 - I/O 41 I/O 42 - I/O 47 I/O 48 - I/O 53 I/O 54 - I/O 59 I/O 60 - I/O 65 I/O 66 - I/O 71 I/O 72 - I/O 77 I/O 78 - I/O 83 I/O 84 - I/O 89 I/O 90 - I/O 95 GOE0, GOE1 J2, J3, K1, L1, K2, M1, L2, K3, N1, M2, L3, P1, M3, P2, N3, M4, P3, N4, P4, M5, N5, P5, M6, N6, N9, M9, P10, P11, N10, P12, N11, M10, P13, N12, M11, P14, M12, N14, M13, L12, M14, L13, L14, K12, K13, K14, J12, J13, F13, F12, E14, D14, E13, C14, D13, E12, B14, C13, D12, A14, C12, A13, B12, C11, A12, B11, A11, C10, B10, A10, C9, B9, B6, C6, A5, A4, B5, A3, B4, C5, A2, B3, C4, A1, C3, B1, C2, D3, C1, D2, D1, E3, E2, E1, F3, F2 Input/Output Pins - These are the general purpose I/O pins used by the logic array. N13, B7, Global output enables for all I/Os. IN 2, IN 4 IN 6 - IN 11 P7, P9 Dedicated input pins to the device. F14, A9, A8, A7, A6, F1 ispEN SDI/IN 01 H2 J1 MODE/IN 11 SDO/IN 31 SCLK/IN 51 P6 P8 J14 Input – Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output – This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input – This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. RESET Y0 Y1 Y2 Y3 H1 G1 G14 H13 H14 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/ or any I/O cell on the device. Dedicated clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. GND VCC B2, B8, B13, C8, H3, H12, M8, N2, N8 C7, G2, G3, G12, G13, M7, N7 1. Pins have dual function capability. Ground (GND) V CC Table 2- 0002C-48C/CPGA 11 11 Page

Páginas	Total 14 Páginas
PDF Descargar	[ Datasheet ISPLSI1048C-70LQ.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ISPLSI1048C-70LQ	In-System Programmable High Density PLD	Lattice

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar