|
|
PDF HD64404BT Data sheet ( Hoja de datos )
| Número de pieza | HD64404BT | |
| Descripción | RISC Engine Peripheral LSI | |
| Fabricantes | Hitachi | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HD64404BT (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
To all our customers
Information regarding change of names mentioned
within this document, to Renesas Technology Corp.
On April 1st 2003 the following semiconductor operations were transferred to
Renesas Technology Corporation: operations covering microcomputer, logic,
analog and discrete devices, and memory chips other than DRAMs (flash
memory, SRAMs etc.).
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other
Hitachi brand names are mentioned in the document, these names have all
been changed to Renesas Technology Corporation.
Except for our corporate trademark, logo and corporate statement, no
changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the
document itself.
Thank you for your understanding.
Renesas Technology Home Page: www.renesas.com
Renesas Technology Corp.
April 1, 2003
Renesas Technology Corp.
1 page  
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
System-Control Modules
On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each
section includes notes in relation to the descriptions given, and usage notes are given, as required,
as the final part of each section.
7. Electrical Characteristics
8. Appendix
9. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
10. Index
Rev. 1.0, 09/02, page iv of xliv
5 Page 
1.8 Detailed Architecture ........................................................................................................ 34
1.8.1 Main Clocking ..................................................................................................... 34
1.8.2 Pixel Bus .............................................................................................................. 43
1.8.3 Register Bus......................................................................................................... 44
1.8.4 System Interface .................................................................................................. 45
1.8.5 PCI ....................................................................................................................... 46
1.8.6 MPX..................................................................................................................... 46
1.8.7 Graphics Memory (SDRAM) Controller ............................................................. 46
1.8.8 Interrupt Controller .............................................................................................. 47
1.8.9 Power Saving ....................................................................................................... 47
1.9 Endian Support ................................................................................................................. 48
1.9.1 Definitions ........................................................................................................... 48
1.9.2 Description........................................................................................................... 48
1.9.3 Register Bus......................................................................................................... 49
1.9.4 Pixel Bus .............................................................................................................. 50
1.9.5 System Types....................................................................................................... 51
1.9.6 Register Bus Summary ........................................................................................ 52
1.9.7 Pixel Bus Summary ............................................................................................. 53
1.10 HD64404 Memory Map.................................................................................................... 54
1.10.1 MPX Mode .......................................................................................................... 54
1.10.2 PCI Mode............................................................................................................. 57
1.11 System Configuration Example ........................................................................................ 60
1.11.1 MPX System Example 1...................................................................................... 60
1.11.2 MPX System Example 2—UMA (Unified Memory Architecture)
Configuration ....................................................................................................... 61
1.11.3 PCI System Example ........................................................................................... 62
Section 2 DMAC ...............................................................................................65
2.1 General Description .......................................................................................................... 65
2.2 Features............................................................................................................................. 66
2.3 Limitations ........................................................................................................................ 67
2.4 Digital Inputs/Outputs....................................................................................................... 70
2.5 Address Map ..................................................................................................................... 70
2.5.1 DMAC Registers.................................................................................................. 73
2.5.2 DMA Channel Registers ...................................................................................... 75
2.5.3 DMA FIFO Channels........................................................................................... 78
2.5.4 DMA Request Numbers....................................................................................... 79
2.6 Register Description.......................................................................................................... 81
2.6.1 DMA Channel Registers (DMA Channel Number n = 0 to 15)........................... 81
2.6.2 DMA Peripheral Request Registers (DMA Request Number q = 0 to 30) .......... 98
2.6.3 DMA Configuration and Status Registers............................................................ 99
2.7 Functional Description...................................................................................................... 111
2.7.1 DMA Data Transfer ............................................................................................. 111
Rev. 1.0, 09/02, page x of xliv
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD64404BT.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HD64404BT | RISC Engine Peripheral LSI | Hitachi |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |