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PDF HD643303x Data sheet ( Hoja de datos )
| Número de pieza | HD643303x | |
| Descripción | Hitachi Microcomputer | |
| Fabricantes | Hitachi | |
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Hay una vista previa y un enlace de descarga de HD643303x (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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OMC942723169
Hitachi Microcomputer
H8/3032 Series
Hardware Manual
1 page  
Contents
Section 1 Overview ..................................................................................................... 1
1.1 Overview ........................................................................................................................ 1
1.2 Block Diagram................................................................................................................ 5
1.3 Pin Description ............................................................................................................... 6
1.3.1 Pin Arrangement............................................................................................. 6
1.3.2 Pin Functions .................................................................................................. 7
1.4 Pin Functions .................................................................................................................. 10
Section 2 CPU ............................................................................................................... 15
2.1 Overview ........................................................................................................................ 15
2.1.1 Features........................................................................................................... 15
2.1.2 Differences from H8/300 CPU ....................................................................... 16
2.2 CPU Operating Modes.................................................................................................... 17
2.3 Address Space................................................................................................................. 18
2.4 Register Configuration.................................................................................................... 19
2.4.1 Overview......................................................................................................... 19
2.4.2 General Registers............................................................................................ 20
2.4.3 Control Registers ............................................................................................ 21
2.4.4 Initial CPU Register Values ............................................................................ 22
2.5 Data Formats................................................................................................................... 23
2.5.1 General Register Data Formats....................................................................... 23
2.5.2 Memory Data Formats.................................................................................... 24
2.6 Instruction Set................................................................................................................. 26
2.6.1 Instruction Set Overview ................................................................................ 26
2.6.2 Instructions and Addressing Modes................................................................ 27
2.6.3 Tables of Instructions Classified by Function ................................................ 28
2.6.4 Basic Instruction Formats ............................................................................... 38
2.6.5 Notes on Use of Bit Manipulation Instructions .............................................. 39
2.7 Addressing Modes and Effective Address Calculation .................................................. 39
2.7.1 Addressing Modes .......................................................................................... 39
2.7.2 Effective Address Calculation ........................................................................ 42
2.8 Processing States ............................................................................................................ 46
2.8.1 Overview......................................................................................................... 46
2.8.2 Program Execution State ................................................................................ 47
2.8.3 Exception-Handling State............................................................................... 47
2.8.4 Exception-Handling Sequences ...................................................................... 49
2.8.5 Reset State ...................................................................................................... 50
2.8.6 Power-Down State .......................................................................................... 50
5 Page 
10.3.3 Timing of Setting of Overflow Flag (OVF).................................................... 307
10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ............................. 308
10.4 Interrupts ........................................................................................................................ 309
10.5 Usage Notes .................................................................................................................... 309
Section 11 Serial Communication Interface........................................................... 311
11.1 Overview ........................................................................................................................ 311
11.1.1 Features........................................................................................................... 311
11.1.2 Block Diagram................................................................................................ 313
11.1.3 Input/Output Pins............................................................................................ 314
11.1.4 Register Configuration.................................................................................... 314
11.2 Register Descriptions...................................................................................................... 315
11.2.1 Receive Shift Register (RSR) ......................................................................... 315
11.2.2 Receive Data Register (RDR)......................................................................... 315
11.2.3 Transmit Shift Register (TSR)........................................................................ 316
11.2.4 Transmit Data Register (TDR) ....................................................................... 316
11.2.5 Serial Mode Register (SMR) .......................................................................... 317
11.2.6 Serial Control Register (SCR) ........................................................................ 321
11.2.7 Serial Status Register (SSR) ........................................................................... 325
11.2.8 Bit Rate Register (BRR) ................................................................................. 329
11.3 Operation ........................................................................................................................ 338
11.3.1 Overview......................................................................................................... 338
11.3.2 Operation in Asynchronous Mode.................................................................. 340
11.3.3 Multiprocessor Communication ..................................................................... 349
11.3.4 Synchronous Operation .................................................................................. 356
11.4 SCI Interrupts.................................................................................................................. 365
11.5 Usage Notes .................................................................................................................... 366
Section 12 A/D Converter............................................................................................ 371
12.1 Overview ........................................................................................................................ 371
12.1.1 Features........................................................................................................... 371
12.1.2 Block Diagram................................................................................................ 372
12.1.3 Input Pins ........................................................................................................ 373
12.1.4 Register Configuration.................................................................................... 374
12.2 Register Descriptions...................................................................................................... 375
12.2.1 A/D Data Registers A to D (ADDRA to ADDRD)........................................ 375
12.2.2 A/D Control/Status Register (ADCSR) .......................................................... 376
12.2.3 A/D Control Register (ADCR) ....................................................................... 379
12.3 CPU Interface ................................................................................................................. 380
12.4 Operation ........................................................................................................................ 381
12.4.1 Single Mode (SCAN = 0) ............................................................................... 381
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD643303x.PDF ] | |
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