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PDF SP5730QP1S Data sheet ( Hoja de datos )
| Número de pieza | SP5730QP1S | |
| Descripción | 1.3GHz Low Phase Noise Frequency Synthesiser | |
| Fabricantes | Mitel Networks | |
| Logotipo |  |
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SP5730
1.3GHz Low Phase Noise Frequency Synthesiser
Preliminary Information
DS4877
issue 1.9
July 1999
Features
q Complete 1.3GHz single chip system for
Digital Terrestrial Television applications
q Selectable reference division ratio, compatible
with (DTT) requirements
q Optimised for low phase noise, with
comparison frequencies up to 4MHz
q No RF prescaler
q Selectable reference/comparison frequency
output
q Four selectable I2C bus address
q I2C fast mode compliant and compatible with
3.3 and 5V logic levels
q Four switching ports
q ESD protection, (Normal ESD Handling
procedures should be observed)
Applications
q Digital Satellite ,Cable and Terrestrial tuning
systems
q Communications systems
Ordering Information
SP5730A/KG/MP1S Sticks
SP5730A/KG/MP1T Tape and Reel
SP5730A/KG/QP1S Sticks
SP5730A/KG/QP1T Tape amd Reel
Description
The SP5730 is a single chip frequency synthesiser
designed for tuning systems up to 1.3GHz and is
optimised for digital terrestrial applications.
The RF preamplifier interfaces direct with the RF
programmable divider, which is of MN+A construction
so giving a step size equal to the loop comparison
frequency and no prescaler phase noise degradation
over the RF operating range.
The comparison frequency is obtained either from an
on-chip crystal controlled oscillator, or from an external
source. The oscillator frequency, Fref, or phase
comparator frequency, Fcomp, can be switched to the
REF/COMP output providing a reference frequency for
a second frequency synthesiser.
The synthesiser is controlled via an I2C bus and is fast
mode compliant. It can be hard wired to respond to one
of four addresses to enable two or more synthesisers to
be used on a common bus.
The device contains four switching ports P0-P3.
1 page  
Preliminary Information
Absolute Maximum Ratings
All voltages are referred to Vee at 0V
Characteristic
Min
Supply voltage, Vcc
-0.3
RF input voltage
All I/O port DC offsets
-0.3
SDA and SCL DC offset
-0.3
Storage temperature
-55
Junction temperature
QP16 thermal resistance,
chip to ambient
chip to case
Power consumption at
Vcc = 5.5V
ESD protection
2
Max
7
2.5
Vcc+0.3
6V
+150
150
80
20
83
Units
V
Vpp
V
oV
oC
C
°C/W
°C/W
mW
kV
SP5730
Conditions
Transient
Differential
All ports off
mil std 883 latest revision method 3015
class 1
Functional Description
The SP5730 contains all the elements necessary, with
the exception of a frequency reference, loop filter and
external high voltage transistor, to control a varicap
tuned local oscillator, so forming a complete PLL
frequency synthesised source. The device allows for
operation with a high comparison frequency and is
fabricated in high speed logic, which enables the
generation of a loop with good phase noise performance.
It can also be operated with comparison frequencies
appropriate for frequency offsets as required in digital
terrestrial (DTT) receivers The block diagram is shown
in Figure 2.
The RF input signal is fed to an internal preamplifier,
which provides gain and reverse isolation from the
divider signals. The output of the preamplifier interfaces
direct with the 15-bit fully programmable divider, which
is of MN+A architecture, where the dual modulus
prescaler is 8/9, the A counter is 3-bits, and the M
counter is 12 bits.
The output of the programmable divider is fed to the
phase comparator where it is compared in both phase
and frequency domain with the comparison frequency.
This frequency is derived either from the on-board
crystal controlled oscillator or from an external reference
source. In both cases the reference frequency is divided
down to the comparison frequency by the reference
divider which is programmable into 1 of 29 ratios as
detailed in Table 1.
The output of the phase detector feeds a charge pump
and loop amplifier section, which when used with an
external high voltage transistor and loop filter, integrates
the current pulses into the varactor line voltage.
The programmable divider output Fpd divided by two
can be switched to port P0 by programming the device
into test mode. The test modes are described in Table 4.
Programming
The SP5730 is controlled by an I2C data bus and is
compatible with both standard and fast mode formats
and with I2C data generated from nominal 3.3V and 5V
sources. The I2C logic level is selected by the bi-directional
port P3/LOGLEV. 5V logic levels are selected by
connecting P3/LOGLEV to Vcc or leaving open circuit
and 3.3V by connecting to ground. If this port is used as
an input the P3 data should be programmed to high
impedance. If used as an output 5V logic only levels can
be used and in this case the logic state imposed by the
port on the input is ignored.
Data and Clock are fed in on the SDA and SCL lines
respectively as defined by I2C bus format. The synthesiser
can either accept data (write mode), or send data (read
mode). The LSB of the address byte (R/W) sets the
device into write mode if it is low, and read mode if it is
high. Table 2 illustrates the format of the data. The
device can be programmed to respond to several
addresses, which enables the use of more than one
synthesiser in an I2C bus system. Table 3 shows how the
address is selected by applying a voltage to the ‘address’
input.
5
5 Page 
Preliminary Information
SP5730
11
11 Page | ||
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| PDF Descargar | [ Datasheet SP5730QP1S.PDF ] | |
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