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SP5730MP1S の電気的特性と機能

SP5730MP1SのメーカーはMitel Networksです、この部品の機能は「1.3GHz Low Phase Noise Frequency Synthesiser」です。


製品の詳細 ( Datasheet PDF )

部品番号 SP5730MP1S
部品説明 1.3GHz Low Phase Noise Frequency Synthesiser
メーカ Mitel Networks
ロゴ Mitel Networks ロゴ 




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SP5730MP1S Datasheet, SP5730MP1S PDF,ピン配置, 機能
SP5730
1.3GHz Low Phase Noise Frequency Synthesiser
Preliminary Information
DS4877
issue 1.9
July 1999
Features
q Complete 1.3GHz single chip system for
Digital Terrestrial Television applications
q Selectable reference division ratio, compatible
with (DTT) requirements
q Optimised for low phase noise, with
comparison frequencies up to 4MHz
q No RF prescaler
q Selectable reference/comparison frequency
output
q Four selectable I2C bus address
q I2C fast mode compliant and compatible with
3.3 and 5V logic levels
q Four switching ports
q ESD protection, (Normal ESD Handling
procedures should be observed)
Applications
q Digital Satellite ,Cable and Terrestrial tuning
systems
q Communications systems
Ordering Information
SP5730A/KG/MP1S Sticks
SP5730A/KG/MP1T Tape and Reel
SP5730A/KG/QP1S Sticks
SP5730A/KG/QP1T Tape amd Reel
Description
The SP5730 is a single chip frequency synthesiser
designed for tuning systems up to 1.3GHz and is
optimised for digital terrestrial applications.
The RF preamplifier interfaces direct with the RF
programmable divider, which is of MN+A construction
so giving a step size equal to the loop comparison
frequency and no prescaler phase noise degradation
over the RF operating range.
The comparison frequency is obtained either from an
on-chip crystal controlled oscillator, or from an external
source. The oscillator frequency, Fref, or phase
comparator frequency, Fcomp, can be switched to the
REF/COMP output providing a reference frequency for
a second frequency synthesiser.
The synthesiser is controlled via an I2C bus and is fast
mode compliant. It can be hard wired to respond to one
of four addresses to enable two or more synthesisers to
be used on a common bus.
The device contains four switching ports P0-P3.

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SP5730MP1S pdf, ピン配列
Preliminary Information
SP5730
Electrical Characteristics
Tamb= -40oC to 85oC, VCC= 4.5 to 5.5V
These characteristics are guaranteed by either production test or design. They apply within the specified
ambient temperature and supply voltage unless otherwise stated.
Characteristic
Supply current
RF input voltage
RF input voltage
RF input impedance
SDA, SCL
Input high voltage
Input low voltage
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
Hysteresis
SDA output voltage
SCL clock rate
Charge pump output
current
Charge pump output
leakage
Charge pump drive
output current
Crystal frequency
Recommended crystal
series resistance
External reference input
Frequency
External reference drive
level
Pin
Value
Units
Min Typ Max
20 mA
Conditions
13,14 12.5
300 mVrms 100 MHz – 1.3GHz, see Figure. 4
13,14 40
300 mVrms 50MHz - 100MHz, see Figure 4
13,14
See Figure. 5
4, 5
3
0
2.3
0
5.5 V 5V I2C logic selected
1.5 V 5V I2C logic selected
3.5 V 3V3 I2C logic selected
1 V 3V3 I2C logic selected
10 µA Input voltage =Vcc
10 µA Input voltage = Vee
10 µA Vee = Vcc
0.4 V
4 0.4 V Isink = 3mA
0.6 V Isink = 6mA
5 400 kH
1 See Table 6 Vpin1 = 2V
1
3 10
nA Vpin1 = 2V, Vcc = 5V, +25°C
16 0.5
mA Vpin16 = 0.7V
2,3 2
10
32
3 0.2
20 MHz See Figure 3 for application
200 4 MHz “parallel resonant”
crystal.
20 MHz Sinewave coupled through
10 nF blocking capacitor
0.5 Vpp Sinewave coupled through
10 nF blocking capacitor
3


3Pages


SP5730MP1S 電子部品, 半導体
SP5730
Preliminary Information
When the device receives a valid address byte, it pulls
the SDA line low during the acknowledge period, and
during following acknowledge periods after further data
bytes are received. When the device is programmed into
read mode, the controller accepting the data must pull the
SDA line low during all status byte acknowledge periods
to read another status byte. If the controller fails to pull the
SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.
Write mode
With reference to Table 2, bytes 2 and 3 contain
frequency information bits 214-20 inclusive. Byte 4 and
byte 5 control the reference divider ratio, see Table 1,
charge pump setting, see Table 6, REF/COMP output,
seeTable 7, output ports and test modes, see Table 4.
After reception and acknowledgement of a correct ad-
dress (byte 1), the first bit of the following byte determines
whether the byte is interpreted as a byte 2 or 4, a logic ‘0’
indicating byte 2, and a logic ‘1’ indicating byte 4. Having
interpreted this byte as either byte 2 or 4 the following
data byte will be interpreted as byte 3 or 5 respectively.
Having received two complete data bytes, additional
data bytes can be entered, where byte interpretation
follows the same procedure, without readdressing the
device. This procedure continues until a STOP condition
is received. The STOP condition can be generated after
any data byte, if however it occurs during a byte transmis-
sion, the previous byte data is retained. To facilitate
smooth fine tuning, the frequency data bytes are only
accepted by the device after all 15 bits of frequency data
have been received, or after the generation of a STOP
condition.
Read mode
When the device is in read mode, the status byte read
from the device takes the form shown in Table 2.
Bit 1 (POR) is the power-on reset indicator, and this is set
to a logic ‘1’ if the Vcc supply to the device has dropped
below 3V (at 25°C), e.g. when the device is initially turned
ON. The POR is reset to ‘0’ when the read sequence is
terminated by a STOP command. When POR is set high
this indicates that the programmed information may
have been corrupted and the device reset to power up
condition.
Bit 2 (FL) indicates whether the device is phase locked,
a logic ‘1’ is present if the device is locked, and a logic ‘0’
if the device is unlocked.
Programmable features
RF programmable
divider
Function as described above
Reference programmable
divider
Function as described above.
Charge pump current
The charge pump current can be pro
grammed by bits C1-C0 within data byte
5, as defined in Table 6.
Test mode
The test modes are invoked by bits REB.
RS, T1 and T0 as described in Table 4.
Reference/Comparison
frequency output
The reference frequency Fref or
comparison frequency Fcomp can be
switched to the REF/COMP output,
function as defined in Table 7.
RE and RS default to logic ‘I’ during
device power up, thus enabling the
comparison frequency Fcomp at the
REF/COMP output.
6

6 Page



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共有リンク

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部品番号部品説明メーカ
SP5730MP1S

1.3GHz Low Phase Noise Frequency Synthesiser

Mitel Networks
Mitel Networks
SP5730MP1T

1.3GHz Low Phase Noise Frequency Synthesiser

Mitel Networks
Mitel Networks


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