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PDF SP5669KGMP1S Data sheet ( Hoja de datos )
| Número de pieza | SP5669KGMP1S | |
| Descripción | 2.7GHz I2C Bus Controlled Synthesiser | |
| Fabricantes | Mitel Networks | |
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SP5669
2.7GHz I2C Bus Controlled Synthesiser
Preliminary Information
DS4852 -
Issue 2.1
May 1999
Features
q Complete 2.7GHz single chip system
q Compatible with UK DTT offset requirements
q Optimised for low phase noise
q Selectable divide by two prescaler
q Selectable reference division ratio
q Selectable reference/comparison frequency output
q Selectable charge pump current
q Four selectable I2C bus address
q 5–level ADC
q Pin compatible with the SP5658 3–wire bus
controlled synthesiser and SP5659 I2C bus
synthesiser and SP5659 I2C bus synthesiser
ESD protection; (Normal ESD handling
procedures should be observed)
Applications
q Complete 2.7GHz single chip system
q Optimised for low phase noise
Ordering Information
SP5669/KG/MP1S (Tubes)
SP5669/KG/MP1T (Tape and reel)
The comparison frequency is obtained either from an
on–chip crystal controlled oscillator, or from an external
source. The oscillator frequency Fref or the comparison
frequency F may be switched to the REF/COMP
comp
output. This feature is ideally suited to providing the
reference frequency for a second synthesiser such as in
a double conversion tuner (see Fig. 8).
The synthesiser is controlled via an I 2 C bus, and
responds to one of four programmable addresses which
are selected by applying a specific voltage to the
‘address’ input. This feature enables two or more
synthesisers to be used in a system.
Description
The SP5669 is a single chip frequency synthesiser
designed for tuning systems up to 2.7GHz and offers
step size compatible with DTT offset requirements.
The RF preamplifier drives a divide by two prescaler
which can be disabled for applications up to 2GHz,
allowing direct interfacing with the programmable
divider so enabling a step size equal to the comparison
frequency. For applications up to 2.7GHz the divide by
two is enabled, giving a step size of twice the
comparison frequency.
The device contains four switching ports P0–P3 and a
5–level ADC. The output of the ADC can be read via the
I2 C
bus.
The device also contains a varactor line disable and
chargepump disable facility.
1 page  
SP5669
Functional Description
The SP5669 contains all the elements necessary, with the
exception of a frequency reference, loop filter and external
high voltage transistor, to control a varicap tuned local
oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with
a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with
good phase noise performance. The block diagram is
shown in Fig. 2.
The RF input signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider
signals. The output of the preamplifier interfaces with the
17–bit fully programmable divider via a divide–by–two
prescaler. For applications up to 2GHz RF input, the
prescaler may be disabled so eliminating the degradation
in phase noise due to prescaler action. The divider is of
MN+A architecture, where the dual modulus prescaler is
16/17, the A counter is 4–bits, and the M counter is 13–bits.
The output of the programmable divider is fed to the phase
comparator where it is compared in both phase and
frequency domain with the comparison frequency. This
frequency is derived either from the on–board crystal
controlled oscillator or from an external reference source.
In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which
is programmable into 1 of 15 ratios as detailed in Fig. 3.
The output of the phase detector feeds a charge pump and
loop amplifier section, which when used with an external
voltage transistor and loop filter, integrates the current
pulses into the varactor line voltage. By invoking the
device test modes as described in Fig. 5, the varactor drive
output can be disabled so switching the external transistor
’off’ and allowing an external voltage to be written to the
varactor line for tuner alignment purposes. Similarly, the
charge pump may be also disabled to a high impedance
state.
The programmable divider output Fpd/2 can be switched
to port P0 by programming the device into test mode. The
test modes are described in Fig. 5 high
Programming
The SP5669 is controlled by an I 2 C data bus. Data
and Clock are fed in on the SDA and SCL lines
respectively as defined by I2C bus format. The
synthesiser can either accept data (write mode) or
send data (read mode). The LSB of the address byte
(R/W) sets the device into write mode if it is low, and
read mode if it is high. Tables 1 and 2 in Fig. 4 illustrate
the format of the data. The device can be
programmed to respond to several addresses, which
enables the use of more than one synthesiser in an
I2C bus system. Table 3 in Fig.4 shows how the
address is selected by applying a voltage to the
’address’ input. When the device receives a valid
address byte, it pulls the SDA line low during the
acknowledge period, and during following
acknowledge periods after further data bytes are
received. When the device is programmed into read
mode, the controller accepting the data must pull the
SDA line low during all status byte acknowledge
periods to read another status byte. If the controller
fails to pull the SDA line low during this period, the
device generates an internal STOP condition, which
inhibits further reading.
Write Mode
With reference to Table 1, bytes 2 and 3 contain
frequency information bits 2 14 –2 0 inclusive.
Auxillary frequency bits 2 16 –2 15 are in byte 4. For
most frequencies only bytes 2 and 3 will be required.
The remainder of byte 4 and byte 5 control the
prescaler enable, reference divider ratio (see Fig. 3),
charge pump, REF/COMP output (see Fig. 5), output
ports and test modes (see Fig. 5).
After reception and acknowledgement of a correct
address (byte 1), the first bit of the following byte
determines whether the byte is interpreted as a byte
2 or 4, a logic ’0’ indicating byte 2 and a logic ’1’
indicating byte 4. Having interpreted this byte as
either byte 2 or 4 the following data byte will be
interpreted as byte 3 or 5 respectively. Having
received two complete data bytes, additional data
bytes can be entered, where byte interpretation
follows the same procedure, without readdressing
the device. This procedure continues until a STOP
condition is received. The STOP condition can be
generated after any data byte, if however it occurs
during a byte transmission, the previous data is
retained.
5
5 Page 
Loop Bandwidth
The majority of applications for which the SP5669 is
intended require a loop filter bandwidth of between
2kHz and10kHz.
Typically the VCO phase noise will be specified at both
1kHz and10kHz offset. It is common practice to arrange
the loop filter bandwidth such that the 1kHz figure lies
within the loop bandwidth. Thus the phase noise de-
pends on the synthesiser comparator noise floor, rather
than the VCO.
The 10kHz offset figure should depend on the VCO
providing the loop is designed correctly, and is not
underdamped.
Reference Source
The SP5669 offers optimal LO phase noise perform-
ance when operated with a large step size. This is due
to the fact that the LO phase noise within the loop
bandwidth is:
phase comparator
LO frequency
( )noise floor + 20 log 10 phase comparator frequency
Assuming the phase comparator noise floor is flat
irrespective of sampling frequency, this means that the
best performance will be achieved when the overall LO
to phase comparator division ratio is a minimum.
SP5669
There are two ways of achieving a higher phase compa-
rator sampling frequency:–
A) Reduce the division ratio between the reference
source and the phase comparator
B) use a higher reference source frequency.
Approach B) may be preferred for best performance
since it is possible that the noise floor of the reference
oscillator may degrade the phase comparator perform-
ance if the reference division ratio is very small.
Driving Two Devicesfrom A Common
Reference
As mentioned earlier in the Datasheet, the SP5669 has
a REF/COMP output which allows two synthesisers to
be driven from a common reference. To do this, the
‘‘Master” should be programmed by setting RE = 1 and
RTS = 0. The driven device should be programmed for
normal operation i.e. RE = 0, and RTS = 0. The two
devices should be connected as shown below.
11
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| PDF Descargar | [ Datasheet SP5669KGMP1S.PDF ] | |
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