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PDF SP5512 Data sheet ( Hoja de datos )
| Número de pieza | SP5512 | |
| Descripción | 1.3GHz Bidirectional I2C BUS Controlled Synthesiser | |
| Fabricantes | Mitel Networks | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SP5512 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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SP5512
1.3GHz Bidirectional I2C BUS Controlled Synthesiser
Supersedes version in April 1994 Consumer IC Handbook, HB3120 - 2.0
DS2384 - 4.0 January 1997
The SP5512 is a single-chip frequency synthesiser designed
for TV tuning systems. Control data is entered in the standard
I2C BUS format. The device has six controllable open-collector
output ports (P2-P7), each capable of sinking 20mA. In addition,
P6 is a 3-bit 5-level ADC input. The information on these ports
can be read via the I2C BUS.
The device has one fixed I2C BUS address and three
programmable addresses, allowing two or more synthesisers
to be used in a system.
FEATURES
s Complete 1·3GHz Single Chip System
s Programmable via the I2C BUS
s Low Power Consumption (215mW Typ.)
s Low Radiation
s Phase Lock Detector
s Varactor Drive Amp Disable
s 6 Controllable Outputs, 5 Bi-directional
s 5-Level ADC
s Variable I2C BUS Address for Picture in Picture TV
s ESD Protection *
* Normal ESD handling precautions should be observed.
Fig. 1 Pin connections – top view
APPLICATIONS
s Cable Tuning Systems
s VCRs
ORDERING INFORMATION
SP5512S KG MPAS (16-lead miniature plastic package)
1 page  
SP5512
MSB
LSB
Address
Programmable divider
Programmable divider
1 1 0 0 0 MA1 MA0 0
0 214 213 212 211 210 29 28
27 26 25 24 23 22 21 20
Charge pump and test bits 1 CP T1 T0 1 1 1 OS
I/O port control bits
P7 P6 P5 P4 P3 P2 X X
Table 1 Write data format (MSB transmitted first)
A
A
A
A
A
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Address
Status byte
1 1 0 0 0 MA1 MA0 1 A Byte 1
POR FL I2 I1 I0 A2 A1 A0 A Byte 2
Table 2 Read data format
A2 A1 A0 Voltage input to P6
1 00
0·6VCC to 13·2V
0 11
0·45VCC to 0·6VCC
0 10
0·3VCC to 0·45VCC
0 01
0·15VCC to 0·3VCC
0 00
0V to 0·15VCC
Table 3 ADC levels
MA1 MA0 Voltage input to P3
00
01
0V to 0·2VCC
Always valid
1 0 0·3VCC to 0·7VCC
1 1 0·8VCC to 13·2V
Table 4 Address selection
A
MA1, MA0
CP
T1
T0
OS
P7, P6, P5, P4,
P3, P2
POR
FL
I2, I1, I0
A2, A1, A0
X
: Acknowledge bit
: Variable address bits (see Table 4)
: Charge Pump current select
: Test mode selection
: Charge pump disable
: Varactor drive Output disable Switch
: Control output port states
: Power On Reset indicator
: Phase lock detect flag
: Digital information from ports P7, P5 and P4 respectively
: 5-level ADC data from P6 (see Table 3)
: Don't care
Fig. 3 Data formats
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet SP5512.PDF ] | |
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