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SP5502 の電気的特性と機能

SP5502のメーカーはMitel Networksです、この部品の機能は「1.3GHz I2C BUS 4-Address Synthesiser」です。


製品の詳細 ( Datasheet PDF )

部品番号 SP5502
部品説明 1.3GHz I2C BUS 4-Address Synthesiser
メーカ Mitel Networks
ロゴ Mitel Networks ロゴ 




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SP5502 Datasheet, SP5502 PDF,ピン配置, 機能
SP5502
1.3GHz I2C BUS 4-Address Synthesiser
Supersedes version in April 1994 Consumer IC Handbook, HB3120 - 2.0
The SP5502 is a single-chip frequency synthesiser designed
for TV tuning systems. Control data is entered in the standard
I2C BUS format. The SP5502 has four programmable I2C BUS
addresses, which allows two or more synthesisers to be used
in a system.
The device is available in two variants: the SP5502F in 14-
lead miniature plastic package (MP14) and the SP5502S in 16-
lead miniature plastic package (MP16). See Features below for
functional differences between the devices.
FEATURES
s Complete 1·3GHz Single Chip System
s Programmable via the I2C BUS
s Low Power Consumption (240mW Typ.)
s Low Radiation
s Phase Lock Detector
s Varactor Drive Amp Disable
s 5320mA Controllable Outputs (SP5502S)
s 3320mA Controllable Outputs (SP5502F)
s Variable I2C BUS Address for Multi-Tuner Applications
s ESD Protection *
* Normal ESD handling precautions should be observed.
DS3031 - 5.0 January 1997
Fig. 1 Pin connections – top view
APPLICATIONS
s Cable Tuning Systems
s VCRs
ORDERING INFORMATION
SP5502F KG MPAS (14-lead miniature plastic package)
SP5502S KG MPAS (16-lead miniature plastic package)
Fig. 2 Block diagram of SP5502S. (Ports P0 and P4 not present on SP5502F)

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SP5502 pdf, ピン配列
The programmed frequency can be calculated by multiply-
ing the programmed division ratio by 8 times the comparison
frequency FCOMP.
When frequency data is entered, the phase comparator,
via the charge pump and varactor drive amplifier, adjusts the
local oscillator control voltage until the output of the program-
mable divider is frequency and phase locked to the comparison
frequency.
The reference frequency may be generated by an external
source capacitively coupled into pin 2 or provided by an on-
chip 4MHz crystal controlled oscillator.
Note that the comparison frequency is 7·8125kHz when a
4MHz reference is used.
Bit 2 of Byte 4 of the programming data (CP) controls the
current in the charge pump circuit, a logic 1 for 6170µA and
a logic 0 for 650µA, allowing compensation for the variable
tuning slope of the tuner and also to enable fast channel
changes over the full band. Bit 4 of Byte 4 (T0) disables the
SP5502
charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches
the charge pump drive amplifier’s output off when it is set to
a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the
phase comparator inputs are available on P2 and P7, a logic
1 connects FCOMP to P2 and FDIV to P7.
Byte 5 programs the output ports P0-P2, P4 and P7 on the
SP5502S (P1, P2 and P7 only on SP5502F), a logic 0 for a
high impedance output, logic 1 for low impedance (on).
READ MODE
When the device is in the read mode the status data read from
the device on the SDA line takes the form shown in Table 2. Bit
1 (POR) is the power supply to the device has dropped below a
nominal 3V and the programmed information lost (e.g., when the
device is initially turned on). The POR is set to 0 when the read
sequence is terminated by a stop command. The outputs are all
set to high impedance when the device is initially powered up. Bit
2 (FL) indicates whether the device is phase locked, a logic 1 is
present if the device is locked and a logic 0 if the device is
unlocked.
MSB
LSB
Address
Programmable divider
Programmable divider
1 1 0 0 0 MA1 MA0 0
0 214 213 212 211 210 29 28
27 26 25 24 23 22 21 20
Charge pump and test bits 1 CP T1 T0 1
I/O port control bits
P7 X X P4* X
1 1 OS
P2 P1 P0*
Table 1 Write data format (MSB transmitted first)
A
A
A
A
A
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Address
Status byte
1 1 0 0 0 MA1 MA0
POR FL N N N N N
Table 2 Read data format
1
N
A Byte 1
A Byte 2
MA1 MA0 Voltage input to P3
00
01
0V to 0·1VCC
Open circuit
1 0 0·4VCC to 0·6VCC
11
0·9VCC to VCC
Table 3 Address selection
A:
MA1, MA0
:
CP :
T1 :
T0 :
OS :
P7, P4*, P2, P1, P0*
POR
:
FL :
X:
N:
Acknowledge bit
Variable address bits (see Table 3)
Charge Pump current select
Test mode selection
Charge pump disable
Varactor drive Output disable Switch
: Control output port states
Power On Reset indicator
Phase lock detect flag
Don’t care
Not valid
NOTES
† Programmed by connecting a 15kresistor between Address Select Port P3 and VCC.
* Don’t care condition on SP5502F.
Fig. 3 Data formats
3


3Pages


SP5502 電子部品, 半導体
SP5502
Fig. 7 Typical input impedance
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE = 0V
Parameter
Supply voltage
RF input voltage
Port voltage
Total port output current
RF input DC offset
Charge pump DC offset
Drive output DC offset
Crystal oscillator DC offset
SDA, SCL input voltage
Storage temperature
Junction temperature
MP16 thermal resistance, chip-to-ambient
MP16 thermal resistance, chip-to-case
MP14 thermal resistance, chip-to-ambient
MP14 thermal resistance, chip-to-case
Power consumption at 5·5V
Pin
SP5502S SP5502F
12
13,14
6,7, 9-11
6,7, 9-11
8
10
11,12
6,8, 9
6,8, 9
7
6,7, 9-11
13,14
1
16
2
4,5
6,8, 9
11,12
1
14
2
4,5
Value
Min.
Max.
Units
Conditions
20·3
20·3
20·3
20·3
20·3
20·3
20·3
20·3
20·3
20·3
255
7
2·5
14
6
VCC10·3
50
VCC10·3
VCC10·3
VCC10·3
VCC10·3
VCC10·3
5·5
1150
1150
111
41
123
45
363
V
V p-p
V
V
V
mA
V
V
V
V
V
V
°C
°C
°C/W
°C/W
°C/W
°C/W
mW
Port in off state
Port in on state
With VCC applied
VCC not applied
6

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Link :


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1.3GHz I2C BUS 4-Address Synthesiser

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