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74HCT158 の電気的特性と機能

74HCT158のメーカーはPhilipsです、この部品の機能は「Quad 2-input multiplexer inverting」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HCT158
部品説明 Quad 2-input multiplexer inverting
メーカ Philips
ロゴ Philips ロゴ 




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74HCT158 Datasheet, 74HCT158 PDF,ピン配置, 機能
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT158
Quad 2-input multiplexer; inverting
Product specification
File under Integrated Circuits, IC06
December 1990

1 Page





74HCT158 pdf, ピン配列
Philips Semiconductors
Quad 2-input multiplexer; inverting
PIN DESCRIPTION
PIN NO.
1
2, 5, 11, 14
3, 6, 10, 13
4, 7, 9, 12
8
15
16
SYMBOL
S
1I0 to 4I0
1I1 to 4I1
1Y to 4Y
GND
E
VCC
NAME AND FUNCTION
common data select input
data inputs from source 0
data inputs from source 1
multiplexer outputs
ground (0 V)
enable input (active LOW)
positive supply voltage
Product specification
74HC/HCT158
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3


3Pages


74HCT158 電子部品, 半導体
Philips Semiconductors
Quad 2-input multiplexer; inverting
Product specification
74HC/HCT158
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To
determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
nI0
nI1
S
E
UNIT LOAD COEFFICIENT
0.40
0.40
2.80
0.60
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HCT
+25 40 to +85
min. typ. max. min. max.
40 to +125
min. max.
UNIT
VCC
(V)
WAVEFORMS
tPHL/ tPLH propagation delay
16 30
38
45 ns 4.5 Fig.7
nI0, nI1 to nY
tPHL/ tPLH propagation delay
19 35
44
53 ns 4.5 Fig.6
E to nY
tPHL/ tPLH propagation delay
19 35
44
53 ns 4.5 Fig.7
S to nY
tTHL/ tTLH output transition 7 15 19 22 ns 4.5 Figs 6 and 7
time
December 1990
6

6 Page



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共有リンク

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