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74HC5555N の電気的特性と機能

74HC5555NのメーカーはPhilipsです、この部品の機能は「Programmable delay timer with oscillator」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HC5555N
部品説明 Programmable delay timer with oscillator
メーカ Philips
ロゴ Philips ロゴ 




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74HC5555N Datasheet, 74HC5555N PDF,ピン配置, 機能
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT5555
Programmable delay timer with
oscillator
Product specification
File under Integrated Circuits, IC06
September 1993

1 Page





74HC5555N pdf, ピン配列
Philips Semiconductors
Programmable delay timer with oscillator
Product specification
74HC/HCT5555
PINNING
SYMBOL
RS
RTC
CTC
A
B
RTR/RTR
Q
GND
Q
S0 S3
OSC CON
MR
VCC
PIN DESCRIPTION
1 clock input/oscillator pin
2 external resistor connection
3 external capacitor connection
4 trigger input (positive-edge
triggered)
5 trigger input (negative-edge
triggered)
6 retriggerable/non-retriggerable
input (active HIGH/active LOW)
7 pulse output (active LOW)
8 ground (0 V)
9 pulse output (active HIGH)
10, 11, programmable input
12, 13
14 oscillator control
15 master reset input (active
HIGH)
16 positive supply voltage
handbook, halfpage
RS 1
R TC 2
C TC 3
A4
B
RTR/
RTR
5
6
Q7
GND 8
5555
16 VCC
15 MR
14
OSC
CON
13 S3
12 S2
11 S1
10 S0
9Q
MGA642
Fig.1 Pin configuration.
handbook, halfpage
10
11
12
13
2
3
14
1
6
4
5
15
X/Y
1
2
4
8
!G
RX
CX
16G17
17
&
0
15
1
I=0
R
S
R
CTRDIVm
[T]
Y=0
Y = 15
+
CT = 0
CT = m R
V16
MGA643
9
7
Fig.2 IEC logic diagram.
September 1993
3


3Pages


74HC5555N 電子部品, 半導体
Philips Semiconductors
Programmable delay timer with oscillator
Product specification
74HC/HCT5555
TEST MODE
Set S3 to a logic LOW level, this will divide the 24 stage counter into three, parallel clocking, 8-stage counters. Set S0,
S1 and S2 to a logic HIGH level, this programs the counter to divide-by 28 (256). Apply a trigger pulse and clock in 255
pulses, this sets all flip-flop stages to a logic HIGH level. Set S3 to a logic HIGH level, this causes the counter to divide-by
224. Clock one more pulse into the RS input, this causes a logic 0 to ripple through the counter and output Q/Q goes from
HIGH-to-LOW level. This method of testing the delay counter is faster than clocking in 224 (16 777 216) clock pulses.
FUNCTION TABLE
MR
H
L
L
INPUTS
A
X
X
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don't care
= LOW-to-HIGH transition
= HIGH-to-LOW transition.
OUTPUTS
BQQ
XLH
X
one HIGH level
one LOW level
output pulse
output pulse
one HIGH level
one LOW level
output pulse
output pulse
September 1993
6

6 Page



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共有リンク

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74HC5555

Programmable delay timer with oscillator

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Programmable delay timer with oscillator

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74HC5555N

Programmable delay timer with oscillator

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