PDF 74HC148 Data sheet ( Hoja de datos )

Número de pieza	74HC148
Descripción	8-3 Line Priority Encoder
Fabricantes	Fairchild
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No Preview Available ! October 1987 Revised February 1999 MM74HC148 8-3 Line Priority Encoder General Description The MM74HC148 priority encoder utilizes advanced sili- con-gate CMOS technology. It has the high noise immunity and low power consumption typical of CMOS circuits, as well as the speeds and output drive similar to LB-TTL. This priority encoder accepts 8 input request lines 0–7 and outputs 3 lines A0–A2. The priority encoding ensures that only the highest order data line is encoded. Cascading cir- cuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry. All data inputs and outputs are active at the low logic level. All inputs are protected from damage due to static dis- charge by internal diode clamps to VCC and ground. Features s Typical propagation delay: 13 ns s Wide supply voltage range: 2V–6V Ordering Code: Order Number Package Number Package Description MM74HC148M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74HC148MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC148N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC and TSSOP Inputs Outputs EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO HXXXXXXXX H H H H H L HHHHHHHH H H H H L L XXXXXXXL L L L L H L XXXXXXLH L L H L H L XXXXX LHH L H L L H L XXXX LHHH L H H L H L XXX LHHHH H L L L H L XX LHHHHH H L H L H L X LHHHHHH H H L L H L LHHHHHHH H H H L H H = HIGH L = LOW X = Irrelevant © 1999 Fairchild Semiconductor Corporation DS009390.prf www.fairchildsemi.com 1 page AC Electrical Characteristics Symbol tPHL, tPLH Parameter Maximum Propagation Delay, Any Input to Any Output Conditions Typ Guaranteed Limits Units 14 ns AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC TA = 25°C Typ TA = −40°C to +85°C TA = −55°C to +125°C Units Guaranteed Limits tPHL, tPLH Inputs 0–7 to Outputs 2.0V 4.5V 14 140 28 175 35 210 ns 42 ns A0, A1, A2 6.0V 24 30 36 ns tPHL, tPLH Inputs 0–7 to 2.0V 4.5V 15 140 28 175 35 210 ns 42 ns Output EO 6.0V 24 30 36 ns tPHL, tPLH Inputs 0–7 to 2.0V 4.5V 17 160 32 200 40 240 ns 48 ns Output GS 6.0V 27 34 41 ns tPHL, tPLH Input EI to Outputs 2.0V 4.5V 17 160 32 200 40 240 ns 48 ns A0, A1, A2 6.0V 27 34 41 ns tPHL, tPLH Input EI to 2.0V 4.5V 12 100 20 125 25 150 ns 30 ns Output GS 6.0V 17 21 26 ns tPHL, tPLH Input EI to 2.0V 4.5V 12 100 20 125 25 150 ns 30 ns Output EO 6.0V 17 21 26 ns tf, tr Maximum Output Rise 2.0V 4.5V 7 75 15 95 19 110 ns 22 ns and Fall Time 6.0V 13 16 19 ns Cpd Power Dissipation Capacitance (Note 5) 52 pF Cin Maximum Input Capacitance 5 10 10 10 pF Note 5: Cpd determines the no load dynamic power consumption, and the no load dynamic current consumption. 5 www.fairchildsemi.com 5 Page

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