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74FR25900SSC の電気的特性と機能

74FR25900SSCのメーカーはFairchildです、この部品の機能は「9-Bit / 3-Port Latchable Datapath Multiplexer with 25W Output Series Resistors」です。


製品の詳細 ( Datasheet PDF )

部品番号 74FR25900SSC
部品説明 9-Bit / 3-Port Latchable Datapath Multiplexer with 25W Output Series Resistors
メーカ Fairchild
ロゴ Fairchild ロゴ 




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74FR25900SSC Datasheet, 74FR25900SSC PDF,ピン配置, 機能
July 1992
Revised August 1999
74FR25900
9-Bit, 3-Port Latchable Datapath Multiplexer
with 25Output Series Resistors
General Description
The 74FR25900 is a data bus multiplexer routing any of
three 9-bit ports to any other one of the three ports. Read-
back of data latched from any port onto itself is also possi-
ble. The 74FR25900 maintains separate control of all latch-
enable, output enable and select inputs for maximum flexi-
bility. PINV allows inversion of the data from the C8 to A8 or
B8 path. This is useful for control of the parity bit in systems
diagnostics.
This device includes 25resistors in series with A and B
Port outputs. Resistors minimize undershoot and ringing
which may damage or corrupt sensitive device inputs
driven by these ports.
Features
s 25series resistors in the port A and B outputs elimi-
nate the need for external resistors when driving MOS
inputs such as DRAM arrays
s 9-bit data ports for systems carrying parity bits
s Readback capability for system self checks.
s Independent control lines for maximum flexibility
s Guaranteed multiple output switching and 250 pF load
delays
s Outputs optimized for dynamic bus drive capability
s PINV parity control facilitates system diagnostics
s 74FR900 option available without output series resistors
Ordering Code:
Order Number Package Number
Package Description
74FR25900SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Description
Pin Names
LExx
OEx
PINV
S0, S1
A0–A8
B0–B8
C0–C8
Description
Latch Enable Inputs
Output Enable Inputs
Parity Invert Input
Select Inputs
Port A Inputs or 3-STATE Outputs
Port B Inputs or 3-STATE Outputs
Port C Inputs or 3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS011500
www.fairchildsemi.com

1 Page





74FR25900SSC pdf, ピン配列
Logic Diagram
Schematic of A and B Port Outputs
3 www.fairchildsemi.com


3Pages


74FR25900SSC 電子部品, 半導体
Extended AC Electrical Characteristics
TA = 0°C to +70°c
TA = 0°C to +70°c
VCC = +5.0V
VCC = +5.0V
Symbol
Parameter
CL = 50 pF
Nine Outputs
Switching
CL = 250 pF
(Note 6)
Units
(Note 5)
Min Max Min Max
tPLH Propagation Delay
tPHL
An or Bn to Cn
2.0 11.5 4.0 12.5
Cn to An or Bn
tPLH Propagation Delay
tPHL C8 to A8 or B8 (PINV HIGH)
5.5 13.0
tPLH Propagation Delay
tPHL
An to Bn, Bn to An
4.5 16.0 6.0 16.5
tPLH Propagation Delay
tPHL LEAC to Cn, LEBC to Cn
4.5 13.0 5.5 13.5
tPLH Propagation Delay
tPHL LECA to An, LECB to Bn
3.5 11.5 5.5 14.5
tPLH Propagation Delay
tPHL
S0 to Cn
3.0 11.0 3.0 14.0
tPLH Propagation Delay
tPHL
S1 to An or Bn
4.0 16.5 6.5 16.5
tPLH Propagation Delay
tPHL PINV to A8 or B8
4.5 14.5
tPZH
tPZL
Output Enable Time
Cn
1.5 8.0
tPHZ
tPLZ
Output Disable Time
Cn
1.5 6.0
tPZH
tPZL
Output Enable Time
An, Bn
1.5 8.0
tPHZ
tPLZ
Output Disable Time
An, Bn
1.5 7.0
Note 5: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase,
i.e., all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capac-
itors standard AC load. This specification pertains to single output switching only.
www.fairchildsemi.com
6

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部品番号部品説明メーカ
74FR25900SSC

9-Bit / 3-Port Latchable Datapath Multiplexer with 25W Output Series Resistors

Fairchild
Fairchild


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