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PDF 74F8965 Data sheet ( Hoja de datos )
| Número de pieza | 74F8965 | |
| Descripción | 9-Bit address/data Futurebus transceiver / ADT | |
| Fabricantes | Philips | |
| Logotipo |  |
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Philips Semiconductors FAST Products
9-Bit address/data Futurebus transceiver, ADT
Product specification
74F8965/74F8966
FEATURES
• 9–bit transceiver (both directions)
• Drives heavily loaded backplanes with
equivalent load impedances down to
10 ohms
• High drive (100mA) open collector
drivers on B port
• Reduced voltage swing (1V to 2V)
produces less noise and reduces
power consumption
• High speed operation enhances
performance of backplane buses and
facilitates incident wave switching
• Compatible with IEEE 896 futurebus
standards and IEEE 1194 BTL stan-
dard
• Built–in precision band–gap reference
provides accurate receiver thresholds
and improved noise immunity
• Controlled output ramp and multiple
GND pins minimize ground bounce
• Glitch–free power up/power down
operation
• Guaranteed skew of less than 2ns
DESCRIPTION
The 74F8965 and 74F8966 are 9–bit
bidirectional latchable transceivers and are
intended to provide the electrical interface to
a high performance wired–OR bus. The B
port inverting drivers are low–capacitance
open collector with controlled ramp and are
designed to sink 100mA from 2 volts. The B
port inverting receivers have a precision band
gap references for improved noise margins.
The B port interfaces to ’Backplane
Transceiver Logic’ (BTL). BTL features a
reduced (1V to 2V) voltage swing for lower
power consumption and a series diode on
the drivers to reduce capacitive loading.
Incident wave switching is employed, there-
fore BTL propagation delays are short. Al-
though the voltage swing is much less for
BTL, so is its receiver threshold region,
therefore noise margins are excellent.
BTL offers low power consumption, low
ground bounce, EMI and crosstalk, low
capacitive loading, superior noise margin and
low propagation delays. This results in a high
bandwidth, reliable backplane.
The 74F8965 and 74F8966 A ports have TTL
3–state drivers and TTL receivers.
The B ports have standard BTL I/O with
100mA current sink capability. The B–to–A
path is a simple inverted buffered path. When
going from A–to–B the user may choose be-
tween a buffered path or a latching function.
The 74F8966 also has an idle arbitrator/multi-
ple competitors output. The IAMC output
compares, using a wired–OR configuration,
the data on the bus to the latched data pres-
ented to the bus. If the bus data matches the
data presented by the 74F8966 then IAMC is
high. If the data doesn’t match then IAMC
goes low.
TYPE
TYPICAL PROPAGATION DELAY
TYPICAL SUPPLY CURRENT( TOTAL)
74F8965
3.5ns
80mA
74F8966
3.5ns
80mA
ORDERING INFORMATION
DESCRIPTION
44–pin PLCC
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F8965A, N74F8966A
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
A0 – A8
B0 – B8
OEA, OEB0, OEB1
TTL data inputs
Data inputs with threshold circuitry
Output enable inputs
74F (U.L.)
HIGH/LOW
1.0/0.033
5.0/0.167
1.0/0.167
LOAD VALUE
HIGH/LOW
20µA/20µA
100µA/100µA
20µA/100µA
LS
IAREQ
LE
A0 – A8
B0 – B8
IAMC
Latch select (active low) (’F8965)
Idle arbitration request (active low) (’F8965)
Latch enable input (active low)
3–state TTL outputs
Open collector BTL outputs
Idle arbitration/multiple competitors output (’F8966)
1.0/0.167
1.0/0.167
1.0/0.167
150/40
OC/166.7
OC/80
20µA/100µA
20µA/100µA
20µA/100µA
3mA/24mA
OC/100mA
OC/48mA
Notes to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2. OC = Open collector.
December 19, 1990
1
853 1526 01320
1 page  
Philips Semiconductors FAST Products
9-Bit address/data Futurebus transceiver, ADT
Product specification
74F8965/74F8966
LOGIC DIAGRAM FOR 74F8966
OEB0
OEB1
1
44
IAREQ
LE
OEA
23
22
2
4
A0
6
A1
8
A2
10
A3
TTL levels
12
A4
13
A5
15
A6
17
A7
19
A8
Logic VCC = Pin 3, 21
Logic GND = Pin 5, 7, 9, 11, 14, 16, 18
December 19, 1990
DQ
E
DQ
E
DQ
E
DQ
E
DQ
E
DQ
E
DQ
E
DQ
E
DQ
E
5
48mA
open
collector
20
TTL level
IAMC
41 B0
39 B1
37 B2
35 B3
33 B4
BTL levels
31 B5
29 B6
27 B7
25 B8
5 Page 
Philips Semiconductors FAST Products
9-Bit address/data Futurebus transceiver, ADT
Product specification
74F8965/74F8966
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST SWITCH
tPLZ, tPZL closed
All other open
PULSE
GENERATOR
VIN
VCC
VOUT
D.U.T.
RL
RT CL RL
Test circuit for 3–state outputs on A port
VCC
7.0V
7.0V
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
tw
VM
10%
tTHL (tf )
VM
10%
tTLH (tr )
tTLH (tr )
90%
VM
tw
tTHL (tf )
90%
VM
Input pulse definition
90%
AMP (V)
Low V
AMP (V)
10%
Low V
PULSE
GENERATOR
VIN
VOUT
D.U.T.
RU
INPUT PULSE REQUIREMENTS
family
74F amplitude Low V VM rep. rate tw tTLH
tTHL
RT CD
A port 3.0V
0.0V 1.5V 1MHz
B port 3.0V
1.0V 1.5V 1MHz
Test circuit for outputs on B port
DEFINITIONS:
RL =
CL =
RU =
CD =
RT =
Load resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Pull up resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Termination resistance should be equal to ZOUT of pulse generators.
500ns 2.5ns 2.5ns
500ns 4.0ns 4.0ns
December 19, 1990
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 74F8965.PDF ] | |
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