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29109BRA の電気的特性と機能

29109BRAのメーカーはIntersilです、この部品の機能は「16K x 1 Asynchronous CMOS Static RAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 29109BRA
部品説明 16K x 1 Asynchronous CMOS Static RAM
メーカ Intersil
ロゴ Intersil ロゴ 




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29109BRA Datasheet, 29109BRA PDF,ピン配置, 機能
HM-65262
March 1997
16K x 1 Asynchronous
CMOS Static RAM
Features
• Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max
• Data Retention at 2.0V . . . . . . . . . . . . . . . . . . .20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout
• No Clocks or Strobes Required
• Temperature Range . . . . . . . . . . . . . . . +55oC to +125oC
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs-No Pull-Up or Pull-Down Resistors
Required
Ordering Information
Description
The HM-65262 is a CMOS 16384 x 1-bit Static Random
Access Memory manufactured using the Intersil Advanced
SAJI V process. The device utilizes asynchronous circuit
design for fast cycle times and ease of use. The HM-65262
is available in both JEDEC standard 20 pin, 0.300 inch wide
CERDIP and 20 pad CLCC packages, providing high board-
level packing density. Gated inputs lower standby current,
and also eliminate the need for pull-up or pull-down resis-
tors.
The HM-65262, a full CMOS RAM, utilizes an array of six
transistor (6T) memory cells for the most stable and lowest
possible standby supply current over the full military temper-
ature range. In addition to this, the high stability of the 6T
RAM cell provides excellent protection against soft errors
due to noise and alpha particles. This stability also improves
the radiation tolerance of the RAM over that of four transistor
(4T) devices.
PACKAGE
CERDIP
JAN #
SMD#
CLCC (SMD#)
TEMP. RANGE
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
70ns/20µA (NOTE 1) 85ns/20µA (NOTE 1)
HM1-65262B-9
HM1-65262-9
29109BRA
29103BRA
8413203RA
8413201RA
8413203YA
8413201YA
(NOTE 1)
85ns/400µA
-
-
-
-
PKG. NO.
F20.3
F20.3
F20.3
J20.C
NOTE:
1. Access Time/Data Retention Supply Current.
Pinouts
HM-65262 (CERDIP)
TOP VIEW
HM-65262 (CLCC)
TOP VIEW
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
Q8
W9
GND 10
20 VCC
19 A13
18 A12
17 A11
16 A10
15 A9
14 A8
13 A7
12 D
11 E
A2 3
A3 4
A4 5
A5 6
A6 7
Q8
2 1 20 19
18 A12
17 A11
16 A10
15 A9
14 A8
13 A7
9 10 11 12
A0 - A13
Address Input
E Chip Enable/Power Down
Q Data Out
D Data In
VSS/GND Ground
VCC Power (+5)
W Write Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
File Number 3002.2

1 Page





29109BRA pdf, ピン配列
HM-65262
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input or Output Voltage Applied for all grades . . . . . -0.3V to VCC +0.3V
Typical Derating Factor . . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical)
CERDIP Package . . . . . . . . . . . . . . . . . .
66θoJCA/W
13θoJCC/W
CLCC Package. . . . . . . . . . . . . . . . . . . . 75oC/W
18oC/W
Maximum Storage Temperature Range . . . . . . . . . . . . . -65oC to +150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HM-65262B-9, HM-65262-9, HM-65262C-9 . . . . .-40oC to +85oC
DC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-65262B-9, HM-65262-9, HM-65262C-9)
LIMITS
SYMBOL
PARAMETER
MIN
MAX
UNITS
TEST CONDITIONS
ICCSB1 Standby Supply Current
ICCSB
ICCEN
ICCOP
Standby Supply Current
Enabled Supply Current
Operating Supply Current (Note 1)
ICCDR Data Retention Supply Current
ICCDR1 Data Retention Supply Current
VCCDR Data Retention Supply Voltage
-od 50 µA HM-65262B-9, HM-65262-9, IO = 0mA,
E = VCC -0.3V, VCC = 5.5V
- 900 µA HM-65262C-9, IO = 0mA,
E = VCC -0.3V, VCC = 5.5V
- 5 mA E = 2.2V, IO = 0mA, VCC = 5.5V
- 50 mA E = 0.8V, IO = 0mA, VCC = 5.5V
- 50 mA E = 0.8V, IO = 0mA, f = 1MHz,
VCC = 5.5V
- 20 µA HM-65262B-9, HM-65262-9,
VCC = 2.0V, E = VCC
- 400 µA HM-65262C-9, VCC = 2.0V, E = VCC
- 30 µA HM-65262B-9, HM-65262-9,
VCC = 3.0V, E = VCC
- 550 µA HM-65262C-9, VCC = 3.0V, E = VCC
2.0 -
V
II
IOZ
VIL
VIH
VOL
VOH1
VOH2
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage (Note 2)
-1.0
-1.0
-0.3
2.2
-
2.4
VCC -0.4
+1.0
+1.0
0.8
VCC +0.3
0.4
-
-
µA VI = VCC or GND, VCC = 5.5V
µA VIO = VCC or GND, VCC = 5.5V
V VCC = 4.5V
V VCC = 5.5V
V IO = 8.0mA, VCC = 4.5V
V IO = -4.0mA, VCC = 4.5V
V IO = -100µA, VCC = 4.5V
Capacitance TA = +25oC
SYMBOL
PARAMETER
CI Input Capacitance (Note 2)
CIO Input/Output Capacitance (Note 2)
NOTES:
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
MAX
10
12
UNITS
pF
pF
TEST CONDITIONS
f = 1MHz, All measurements are
referenced to device GND
6-3


3Pages


29109BRA 電子部品, 半導体
Timing Waveforms (Continued)
HM-65262
A
(18) TAVEL
E
W
D
(8) TAVAX
(20) TAVEH
(21) TELEH
(22) TWLEH
(23) TDVEH
(19) TEHAX
(24)
TEHDX
(16) TWHQX
(4) TELQX
Q
(15) TWLQZ
(7) TEHQZ
NOTE:
1. In this mode, W rises after E. If W falls before E by a time exceeding TWLQZ (Max) TELQX (Min), and rises after E by a time exceeding
TEHQZ (Max) TWHQZ (Min), then Q will remain in the high impedance state throughout the cycle.
FIGURE 4. WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE)
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are guaran-
teed over temperature. The following rules ensure data
retention:
1. Chip Enable (E) must be held high during data retention;
within VCC to VCC +0.3V.
2. On RAMs which have selects or output enables (e.g., S,
G), one of the selects or output enables should be held in
the deselected state to keep the RAM outputs high
impedance, minimizing power dissipation.
3. Inputs which are to be held high (e.g., E) must be kept
between VCC +0.3V and 70% of VCC during the power
up and down transitions.
4. The RAM can begin operation > 55ns after VCC reaches
the minimum operating voltage (4.5V).
VCC
E
4.5V
DATA RETENTION
MODE
VCC 2.0V
VCC -0.3V TO VCC +0.3V
4.5V
>55ns
FIGURE 5. DATA RETENTION TIMING
6-6

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部品番号部品説明メーカ
29109BRA

16K x 1 Asynchronous CMOS Static RAM

Intersil
Intersil


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