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28F128J3AのメーカーはIntelです、この部品の機能は「3 Volt Intel StrataFlash Memory」です。 |
部品番号 | 28F128J3A |
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部品説明 | 3 Volt Intel StrataFlash Memory | ||
メーカ | Intel | ||
ロゴ | |||
このページの下部にプレビューと28F128J3Aダウンロード(pdfファイル)リンクがあります。 Total 58 pages
3 Volt Intel® StrataFlash™ Memory
28F128J3A, 28F640J3A, 28F320J3A (x8/x16)
Preliminary Datasheet
Product Features
s High-Density Symmetrically-Blocked
Architecture
— 128 128-Kbyte Erase Blocks (128 M)
— 64 128-Kbyte Erase Blocks (64 M)
— 32 128-Kbyte Erase Blocks (32 M)
s High Performance Interface Asynchronous
Page Mode Reads
— 110/25 ns Read Access Time (32 M)
— 120/25 ns Read Access Time (64 M)
— 150/25 ns Read Access Time (128 M)
s 2.7 V–3.6 V VCC Operation
s 128-bit Protection Register
— 64-bit Unique Device Identifier
— 64-bit User Programmable OTP Cells
s Enhanced Data Protection Features
Absolute Protection with VPEN = GND
— Flexible Block Locking
— Block Erase/Program Lockout during
Power Transitions
s Packaging
— 56-Lead TSOP Package
— 64-Ball Intel® Easy BGA Package
s Cross-Compatible Command Support Intel
Basic Command Set
— Common Flash Interface
— Scalable Command Set
s 32-Byte Write Buffer
— 6 µs per Byte Effective Programming
Time
s 12.8M Total Min. Erase Cycles (128 Mbit)
6.4M Total Min. Erase Cycles (64 Mbit)
3.2M Total Min. Erase Cycles (32 Mbit)
— 100K Minimum Erase Cycles per Block
s Automation Suspend Options
— Block Erase Suspend to Read
— Block Erase Suspend to Program
— Program Suspend to Read
s 0.25 µ Intel® StrataFlash™ Memory
Technology
Capitalizing on Intel’s 0.25 µ generation two-bit-per-cell technology, second generation Intel®
StrataFlash™ memory products provide 2X the bits in 1X the space, with new features for mainstream
performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring
reliable, two-bit-per-cell storage technology to the flash market segment.
Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash
memory devices take advantage of over one billion units of manufacturing experience since 1987. As a
result, Intel StrataFlash components are ideal for code and data applications where high density and low
cost are required. Examples include networking, telecommunications, digital set top boxes, audio
recording, and digital imaging.
By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design
migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation
Intel StrataFlash memory (28F640J5 and 28F320J5) devices.
Intel StrataFlash memory components deliver a new generation of forward-compatible software support.
By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel® 0.25 micron ETOX™ VI process technology, Intel StrataFlash memory provides
the highest levels of quality and reliability.
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290667-008
April 2001
1 Page 28F128J3A, 28F640J3A, 28F320J3A
Contents
1.0 Product Overview....................................................................................................... 1
2.0 Principles of Operation............................................................................................ 6
2.1 Data Protection...................................................................................................... 6
3.0 Bus Operations ........................................................................................................... 7
3.1 Read...................................................................................................................... 8
3.2 Output Disable....................................................................................................... 8
3.3 Standby ................................................................................................................. 8
3.4 Reset/Power-Down ............................................................................................... 8
3.5 Read Query ........................................................................................................... 9
3.6 Read Identifier Codes............................................................................................ 9
3.7 Write ...................................................................................................................... 9
4.0 Command Definitions............................................................................................... 9
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
Read Array Command.........................................................................................13
Read Query Mode Command .............................................................................13
4.2.1 Query Structure Output ..........................................................................13
4.2.2 Query Structure Overview ......................................................................14
4.2.3 Block Status Register .............................................................................15
4.2.4 CFI Query Identification String ...............................................................15
4.2.5 System Interface Information .................................................................16
4.2.6 Device Geometry Definition....................................................................17
4.2.7 Primary-Vendor Specific Extended Query Table....................................18
Read Identifier Codes Command ........................................................................19
Read Status Register Command.........................................................................20
Clear Status Register Command.........................................................................22
Block Erase Command........................................................................................22
Block Erase Suspend Command ........................................................................22
Write to Buffer Command....................................................................................23
Byte/Word Program Commands .........................................................................24
Program Suspend Command..............................................................................24
Set Read Configuration Command .....................................................................24
4.11.1 Read Configuration ................................................................................25
Configuration Command .....................................................................................25
Set Block Lock-Bit Commands............................................................................26
Clear Block Lock-Bits Command.........................................................................27
Protection Register Program Command .............................................................27
4.15.1 Reading the Protection Register ............................................................27
4.15.2 Programming the Protection Register ....................................................27
4.15.3 Locking the Protection Register .............................................................28
5.0 Design Considerations ..........................................................................................38
5.1 Three-Line Output Control...................................................................................38
5.2 STS and Block Erase, Program, and Lock-Bit Configuration Polling ..................38
5.3 Power Supply Decoupling ...................................................................................38
5.4 Input Signal Transitions - Reducing Overshoots and Undershoots When Using
Preliminary
iii
3Pages 6 Page | |||
ページ | 合計 : 58 ページ | ||
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部品番号 | 部品説明 | メーカ |
28F128J3 | (28FxxxJ3) Strata Flash Memory | Intel |
28F128J3A | 3 Volt Intel StrataFlash Memory | Intel |
28F128J3A | (28FxxxJ3A) Intel StrataFlash Memory | Intel Corporation |