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28C256 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 28C256
部品説明 32K-Bit Parallel E2PROM
メーカ Catalyst
ロゴ Catalyst ロゴ 



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28C256 Datasheet, 28C256 PDF,ピン配置, 機能
CAT28C256
32K-Bit Parallel E2PROM
FEATURES
s Fast Read Access Times: 120/150ns
s Low Power CMOS Dissipation:
–Active: 25 mA Max.
–Standby: 150 µA Max.
s Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
–5ms Max
s CMOS and TTL Compatible I/O
DESCRIPTION
The CAT28C256 is a fast, low power, 5V-only CMOS
parallel E2PROM organized as 32K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bits signal the start and end of the self-
timed write cycle. Additionally, the CAT28C256 features
hardware and software write protection.
s Hardware and Software Write Protection
s Automatic Page Write Operation:
–1 to 64 Bytes in 5ms
–Page Load Timer
s End of Write Detection:
–Toggle Bit
–DATA Polling
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s Commerical, Industrial and Automotive
Temperature Ranges
The CAT28C256 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
A6–A14
VCC
CE
OE
WE
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
A0–A5
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
32,768 x 8
E2PROM
ARRAY
64 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
5096 FHD F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25020-0A 2/98

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