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27LV256 の電気的特性と機能

27LV256のメーカーはMicrochip Technologyです、この部品の機能は「256K (32K x 8) Low-Voltage CMOS EPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 27LV256
部品説明 256K (32K x 8) Low-Voltage CMOS EPROM
メーカ Microchip Technology
ロゴ Microchip Technology ロゴ 




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27LV256 Datasheet, 27LV256 PDF,ピン配置, 機能
27LV256
256K (32K x 8) Low-Voltage CMOS EPROM
FEATURES
• Wide voltage range 3.0V to 5.5V
• High speed performance
- 200 ns access time available at 3.0V
• CMOS Technology for low power consumption
- 8 mA Active current at 3.0V
- 20 mA Active current at 5.5V
- 100 µA Standby current
• Factory programming available
• Auto-insertion-compatible plastic packages
• Auto ID aids automated programming
• Separate chip enable and output enable controls
• High speed “Express” programming algorithm
• Organized 32K x 8: JEDEC standard pinouts
- 28-pin Dual-in-line package
- 32-pin PLCC package
- 28-pin SOIC package
- 28-pin VSOP package
- Tape and reel
• Data Retention > 200 years
• Available for the following temperature ranges:
- Commercial: 0˚C to +70˚C
- Industrial:
-40˚C to +85˚C
DESCRIPTION
The Microchip Technology Inc. 27LV256 is a low volt-
age (3.0 volt) CMOS EPROM designed for battery
powered applications. The device is organized as a
32K x 8 (32K-Byte) non-volatile memory product. The
27LV256 consumes only 8 mA maximum of active cur-
rent during a 3.0 volt read operation therefore improv-
ing battery performance. This device is designed for
very low voltage applications where conventional 5.0
volt only EPROMS can not be used. Accessing individ-
ual bytes from an address transition or from power-up
(chip enable pin going low) is accomplished in less than
200 ns at 3.0V. This device allows systems designers
the ability to use low voltage non-volatile memory with
today’s' low voltage microprocessors and peripherals
in battery powered applications.
A complete family of packages is offered to provide the
most flexibility in applications. For surface mount appli-
cations, PLCC, VSOP or SOIC packaging is available.
Tape and reel packaging is also available for PLCC or
SOIC packages.
PACKAGE TYPES
PDIP
VPP • 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
O0 11
O1 12
O2 13
VSS 14
28 VCC
27 A14
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 O7
18 O6
17 O5
16 O4
15 O3
PLCC
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
NC 12
O0 13
29 A8
28 A9
27 A11
26 NC
25 OE
24 A10
23 CE
22 O7
21 O6
SOIC
VPP 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
O0 11
O1 12
O2 13
VSS 14
VSOP
OE 22
A11 23
A9 24
A8 25
A13 26
A14 27
VCC 28
VPP 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
28 VCC
27 A14
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 O7
18 O6
17 O5
16 O4
15 O3
21 A10
20 CE
19 O7
18 O6
17 O5
16 O4
15 O3
14 VSS
13 O2
12 O1
11 O0
10 A0
9 A1
8 A2
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS11020F-page 1

1 Page





27LV256 pdf, ピン配列
27LV256
TABLE 1-3: READ OPERATION AC CHARACTERISTICS
AC Testing Waveform: VIH = 2.4V and VIL = 0.45V; VOH = 2.0V VOL = 0.8V
Output Load:
1 TTL Load + 100 pF
Input Rise and Fall Times: 10 ns
Ambient Temperature: Commercial:
Tamb = 0˚C to +70˚C
Industrial:
Tamb = -40˚C to +85˚C
Parameter
Sym
27HC256-20
Min Max
27HC256-25
Min Max
27HC256-30
Min Max
Units
Conditions
Address to Output Delay tACC
200
250 — 300
ns CE = OE = VIL
CE to Output Delay
tCE — 200 — 250 — 300 ns OE = VIL
OE to Output Delay
tOE — 100 — 125 — 125 ns CE = VIL
CE or OE to O/P High
tOFF
0
50
0
50 0 50
ns
Impedance
Output Hold from
Address CE or OE,
whichever goes first
tOH 0 — 0 — 0 — ns
FIGURE 1-1: READ WAVEFORMS
Address
VIH
VIL
Address valid
VIH
CE
VIL
VIH
OE
VIL
Outputs
O0 - O7
VOH
VOL
High Z
tCE(2)
tOE(2)
tACC
tOFF(1,3)
tOH
Valid Output
High Z
Notes: (1) tOFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested.
© 1996 Microchip Technology Inc.
DS11020F-page 3


3Pages


27LV256 電子部品, 半導体
27LV256
1.3 Standby Mode
The standby mode is defined when the CE pin is high
(VIH) and a program mode is not defined. Output Dis-
able
1.4 Output Enable
This feature eliminates bus contention in multiple bus
microprocessor systems and the outputs go to a high
impedance when the following condition is true:
• The OE pin is high and program mode is not
defined.
1.5 Programming Mode
The Express algorithm has been developed to improve
on the programming throughput times in a production
environment. Up to 10 100-microsecond pulses are
applied until the byte is verified. No over-programming
is required. A flowchart of the express algorithm is
shown in Figure 1.
Programming takes place when:
a) VCC is brought to the proper voltage
b) VPP is brought to the proper VH level
c) the OE pin is high
d) the CE pin is low
Since the erased state is “1” in the array, programming
of “0” is required. The address to be programmed is set
via pins A0-A14 and the data to be programmed is pre-
sented to pins O0-O7. When data and address are sta-
ble, a low-going pulse on the CE line programs that
location.
1.6 Verify
After the array has been programmed it must be veri-
fied to ensure that all the bits have been correctly pro-
grammed. This mode is entered when all of the
following conditions are met:
a) VCC is at the proper level
b) VPP is at the proper VH level
c) the CE pin is high
d) the OE line is low
1.7 Inhibit
When Programming multiple devices in parallel with
different data, only CE needs to be under separate con-
trol to each device. By pulsing the CE line low on a par-
ticular device, that device will be programmed, and all
other devices with CE held high will not be pro-
grammed with the data although address and data are
available on their input pins.
1.8 Identity Mode
In this mode specific data is outputted which identifies
the manufacturer as Microchip Technology Inc. and
device type. This mode is entered when Pin A9 is
taken to VH (11.5V to 12.5V). The CE and OE lines
must be at VIL. A0 is used to access any of the two
non-erasable bytes whose data appears on O0 through
O7.
Pin Input Output
Identity
A0 0 O O O O O O O H
76543210 e
x
Manufacturer VIL 0 0 1 0 1 0 0 1 29
Device Type* VIH 1 0 0 0 1 1 0 0 8C
* Code subject to change.
DS11020F-page 6
© 1996 Microchip Technology Inc.

6 Page



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部品番号部品説明メーカ
27LV256

256K (32K x 8) Low-Voltage CMOS EPROM

Microchip Technology
Microchip Technology


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