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27C64 の電気的特性と機能

27C64のメーカーはSTMicroelectronicsです、この部品の機能は「64 Kbit 8Kb x 8 UV EPROM and OTP EPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 27C64
部品説明 64 Kbit 8Kb x 8 UV EPROM and OTP EPROM
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 




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27C64 Datasheet, 27C64 PDF,ピン配置, 機能
M27C64A
64 Kbit (8Kb x 8) UV EPROM and OTP EPROM
5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
FAST ACCESS TIME: 150ns
LOW POWER “CMOS” CONSUMPTION:
– Active Current 30mA
– Standby Current 100µA
PROGRAMMING VOLTAGE: 12.5V ± 0.25V
HIGH SPEED PROGRAMMING
(less than 1 minute)
ELECTRONIC SIGNATURE
– Manufacturer Code: 9Bh
– Device Code: 08h
28
1
FDIP28W (F)
PLCC32 (C)
DESCRIPTION
The M27C64A is a 64Kbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs and is
organized as 8,192 by 8 bits.
The FDIP28W (window ceramic frit-seal package)
has transparent lid which allows the user to expose
the chip to ultraviolet light to erase the bit pattern.
A new pattern can then be written to the device by
following the programming procedure.
For applications where the content is programmed
only on time and erasure is not required, the
M27C64A is offered in PLCC32 package.
Figure 1. Logic Diagram
VCC VPP
13
A0-A12
8
Q0-Q7
Table 1. Signal Names
A0-A12
Address Inputs
Q0-Q7
Data Outputs
E Chip Enable
G Output Enable
P Program
VPP Program Supply
VCC Supply Voltage
VSS Ground
March 1998
P M27C64A
E
G
VSS
AI00834B
1/12

1 Page





27C64 pdf, ピン配列
M27C64A
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable, the address access time
(tAVQV) is equal to the delay from E to output (tELQV).
Data is available at the output after a delay of tGLQV
from the falling edge of G, assuming that E has
been low and the addresses have been stable for
at least tAVQV-tGLQV.
Standby Mode
The M27C64A has a standby mode which reduces
the active current from 30mA to 100µA. The
M27C64A is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high impedance
state, independent of the G input.
Two Line Output Control
Because EPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is required from a particular memory device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at the
output.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between VCC
and VSS. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitor should be used
between VCC and VSS for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
Table 3. Operating Modes
Mode
Read
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Note: X = VIH or VIL, VID = 12V ± 0.5V
E
VIL
VIL
VIL
VIL
VIH
VIH
VIL
G P A9
VIL VIH
VIH VIH
VIH VIL Pulse
VIL VIH
XX
X
X
X
X
X
XXX
VIL VIH VID
VPP Q0 - Q7
VCC Data Out
VCC Hi-Z
VPP Data In
VPP Data Out
VPP Hi-Z
VCC Hi-Z
VCC Codes
Table 4. Electronic Signature
Identifier
A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code
VIL
1
0
0
1
1
0
1
1
Device Code
VIH 0 0 0 0 1 0 0 0
9Bh
08h
3/12


3Pages


27C64 電子部品, 半導体
M27C64A
Table 6. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C: VCC = 5V ± 10%; VPP = VCC)
Symbol
Parameter
Test Condition
Min Max
ILI Input Leakage Current
0V VIN VCC
±10
ILO Output Leakage Current
0V VOUT VCC
±10
ICC Supply Current
E = VIL, G = VIL,
IOUT = 0mA, f = 5MHz
30
ICC1 Supply Current (Standby) TTL
E = VIH
1
ICC2 Supply Current (Standby) CMOS
E > VCC – 0.2V
100
IPP Program Current
VPP = VCC
100
VIL
VIH (2)
Input Low Voltage
Input High Voltage
–0.3
2
0.8
VCC + 1
VOL Output Low Voltage
IOL = 2.1mA
0.4
Output High Voltage TTL
VOH
Output High Voltage CMOS
IOH = –400µA
IOH = –100µA
2.4
VCC – 0.7V
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously with or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
V
Table 7. Read Mode AC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C: VCC = 5V ± 10%; VPP = VCC)
Symbol Alt
Parameter
Test Condition
-15
M27C64A
-20 -25
-30 Unit
Min Max Min Max Min Max Min Max
tAVQV
tACC
Address Valid to
Output Valid
E = VIL, G = VIL
150
200
250
300 ns
tELQV
tCE
Chip Enable Low to
Output Valid
G = VIL
150 200 250 300 ns
tGLQV
tOE
Output Enable Low
to Output Valid
E = VIL
75 80 100 120 ns
tEHQZ (2)
tDF
Chip Enable High to
Output Hi-Z
G = VIL
0 50 0 50 0 60 0 105 ns
tGHQZ (2)
tDF
Output Enable High
to Output Hi-Z
E = VIL
0 50 0 50 0 60 0 105 ns
tAXQX
tOH
Address Transition to
Output Transition
E = VIL, G = VIL
0
0
0
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously with or after VPP.
2. Sampled only, not 100% tested.
0
ns
6/12

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
27C64

64K (8K x 8) CMOS EPROM

Microchip Technology
Microchip Technology
27C64

64 Kbit 8Kb x 8 UV EPROM and OTP EPROM

STMicroelectronics
STMicroelectronics
27C64

64K (8K x 8) CHMOS Production and UV Erasable PROMS

Intel
Intel
27C64A

64K-bit CMOS EPROM(8K x 8)

Philips
Philips


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