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27C17A の電気的特性と機能

27C17AのメーカーはMicrochip Technologyです、この部品の機能は「16K (2K x 8) CMOS EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 27C17A
部品説明 16K (2K x 8) CMOS EEPROM
メーカ Microchip Technology
ロゴ Microchip Technology ロゴ 




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27C17A Datasheet, 27C17A PDF,ピン配置, 機能
28C17A
16K (2K x 8) CMOS EEPROM
FEATURES
• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100 µA Standby
• Fast Byte Write Time—200 µs or 1 ms
• Data Retention >200 years
• High Endurance - Minimum 104 Erase/Write Cycles
• Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data Polling; Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
- VCC Detector
- Pulse Filter
- Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 2Kx8 JEDEC Standard Pinout
- 28 Pin Dual-In-Line Package
- 32-Pin PLCC Package
- 28-Pin Thin Small Outline Package (TSOP)
8x20mm
- 28-Pin Very Small Outline Package (VSOP)
8x13.4mm
• Available for Extended Temperature Ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
DESCRIPTION
The Microchip Technology Inc. 28C17A is a CMOS 16K non-
volatile electrically Erasable PROM. The 28C17A is
accessed like a static RAM for the read or write cycles without
the need of external components. During a “byte write”, the
address and data are latched internally, freeing the micropro-
cessor address and data bus for other operations. Following
the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an
internal control timer. To determine when the write cycle is
complete, the user has a choice of monitoring the Ready/
Busy output or using Data polling. The Ready/Busy pin is an
open drain output, which allows easy configuration in wired-
or systems. Alternatively, Data polling allows the user to read
the location last written to when the write operation is com-
plete. CMOS design and processing enables this part to be
used in systems where reduced power consumption and reli-
ability are required. A complete family of packages is offered
to provide the utmost flexibility in applications.
PACKAGE TYPES
RDY/BSY
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 Vcc
27 WE
26 NC
25 A8 A6 5
24 A9 A5 6
23 NC A4 7
22 OE A3 8
21 A10 A2 9
20 CE A1 10
19 I/O7 A0 11
18
I/O6
NC
I/O0
12
13
17 I/O5
16 I/O4
15 I/O3
29 A8
28 A9
27 NC
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
• Pin 1 indicator on PLCC on top of package
OE 1
NC 2
A9 3
A8 4
NC 5
WE 6
Vcc 7
RDY/BSY
NC
A7
A6
A5
A4
A3
8
9
10
11
12
13
14
28 A10
27 CE
26 I/07
25 I/06
24 I/05
23 I/04
22 I/03
21 Vss
20 I/02
19 I/01
18 I/00
17 A0
16 A1
15 A2
OE
NC
A9
A8
NC
WE
VCC
RDY/BSY
NC
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 VSS
13 I/O2
12 I/O1
11 I/O0
10 A0
9 A1
8 A2
BLOCK DIAGRAM
I/O0 I/O7
VSS
VCC
CE
OE
WE
Rdy/
Busy
A0
A10
Data Protection
Circuitry
Chip Enable/
Output Enable
Control Logic
Auto Erase/Write
Timing
Program Voltage
Generation
Data
Poll
Y
L Decoder
a
t
c
h
eX
s Decoder
Input/Output
Buffers
Y Gating
16K bit
Cell Matrix
© 1996 Microchip Technology Inc.
This document was created with FrameMaker 4 0 4
DS11127G-page 1

1 Page





27C17A pdf, ピン配列
28C17A
TABLE 1-3: READ OPERATION AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 ns
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C
Parameter
Symbol
28C17A-15
Min Max
28C17A-20
Min Max
28C17A-25
Min Max
Units
Conditions
Address to Output Delay
tACC
— 150 — 200 — 250
ns OE = CE = VIL
CE to Output Delay
tCE
— 150 — 200 — 250
ns OE = VIL
OE to Output Delay
tOE — 70 — 80 — 100 ns CE = VIL
CE or OE High to Output
Float
tOFF 0 50 0 55 0 70 ns
Output Hold from Address,
CE or OE, whichever occurs
first.
tOH
0 — 0 — 0 — ns
Endurance
— 1M — 1M — 1M — cycles 25°C, Vcc =
5.0V, Block
Mode (Note)
Note: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1: READ WAVEFORMS
Address
VIH
VIL
VIH
CE
VIL
VIH
OE
VIL
Data
VOH
VOL
VIH
WE
VOL
High Z
Address Valid
tCE(2)
tOE(2)
tACC
tOFF(1,3)
tOH
Valid Output
High Z
Notes: (1) tOFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to t CE - t OE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested
© 1996 Microchip Technology Inc.
DS11127G-page 3


3Pages


27C17A 電子部品, 半導体
28C17A
2.0 DEVICE OPERATION
The Microchip Technology Inc. 28C17A has four basic
modes of operation—read, standby, write inhibit, and
byte write—as outlined in the following table.
Operation
Mode
CE
OE WE
I/O
Rdy/Busy
(1)
Read
L L H DOUT
H
Standby
H X X High Z
H
Write Inhibit H X X High Z
H
Write Inhibit X L X High Z
H
Write Inhibit X X H High Z
H
Byte Write L H L DIN
L
Byte Clear
Automatic Before Each “Write”
Note 1: Open drain output.
2: X = Any TTL level.
2.1 Read Mode
The 28C17A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and is used to gate data to
the output pins independent of device selection.
Assuming that addresses are stable, address access
time (tACC) equal to the delay from CE to output (tCE).
Data is available at the output tOE after the falling edge
of OE, assuming that CE has been low and addresses
have been stable for at least tACC-tOE.
2.2 Standby Mode
The 28C17A is placed in the standby mode by applying
a high signal to the CE input. When in the standby
mode, the outputs are in a high impedance state, inde-
pendent of the OE input.
2.3 Data Protection
In order to ensure data integrity, especially during criti-
cal power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
First, an internal VCC detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation
when VCC is less than the VCC detect circuit trip.
Second, there is a WE filtering circuit that prevents WE
pulses of less than 10 ns duration from initiating a write
cycle.
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (VCC).
2.4 Write Mode
The 28C17A has a write cycle similar to that of a Static
RAM. The write cycle is completely self-timed and ini-
tiated by a low going pulse on the WE pin. On the fall-
ing edge of WE, the address information is latched. On
rising edge, the data and the control pins (CE and OE)
are latched. The Ready/Busy pin goes to a logic low
level indicating that the 28C17A is in a write cycle which
signals the microprocessor host that the system bus is
free for other activity. When Ready/Busy goes back to
a high, the 28C17A has completed writing and is ready
to accept another cycle.
2.5 Data Polling
The 28C17A features Data polling to signal the comple-
tion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the
data complement of I/O7 (I/O0 to I/O6 are indetermin-
able). After completion of the write cycle, true data is
available. Data polling allows a simple read/compare
operation to determine the status of the chip eliminat-
ing the need for external hardware.
2.6 Electronic Signature for Device
Identification
An extra row of 32 bytes of EEPROM memory is avail-
able to the user for device identification. By raising A9
to 12V ±0.5V and using address locations 7EO to 7FF,
the additional bytes can be written to or read from in the
same manner as the regular memory array.
2.7 Chip Clear
All data may be cleared to 1's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.
DS11127G-page 6
© 1996 Microchip Technology Inc.

6 Page



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部品番号部品説明メーカ
27C17A

16K (2K x 8) CMOS EEPROM

Microchip Technology
Microchip Technology


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