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PDF LTC1391IGN Data sheet ( Hoja de datos )
| Número de pieza | LTC1391IGN | |
| Descripción | 8-Channel Analog Multiplexer with Cascadable Serial Interface | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC1391
8-Channel
Analog Multiplexer with
Cascadable Serial Interface
FEATURES
s Low RON: 45Ω
s Single 2.7V to ±5V Supply Operation
s Analog Inputs May Extend to Supply Rails
s Low Charge Injection
s Serial Digital Interface
s Low Leakage: ±5nA Max
s Guaranteed Break-Before-Make
s TTL/CMOS Compatible for All Digital Inputs
s Cascadable to Allow Additional Channels
s Can Be Used as a Demultiplexer
U
APPLICATIONS
s Data Acquisition Systems
s Communication Systems
s Signal Multiplexing/Demultiplexing
DESCRIPTION
The LTC ®1391 is a high performance CMOS 8-to-1 analog
multiplexer. It features a serial digital interface that allows
several LTC1391s to be daisy-chained together, increas-
ing the number of MUX channels available using a single
digital port.
The LTC1391 features a typical RON of 45Ω, a typical
switch leakage of 50pA and guaranteed break-before-
make operation. Charge injection is ±10pC maximum. All
digital inputs are TTL and CMOS compatible when oper-
ated from single or dual supplies. The inputs can with-
stand 100mA fault current.
The LTC1391 is available in 16-pin PDIP, SSOP and
narrow SO packages. For applications requiring 2-way
serial data transmission, see the LTC1390 data sheet.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
3V, 8-Channel 12-Bit ADC
3V
ANALOG
INPUTS
1 S0
2 S1
3 S2
4 S3
5 S4
6 S5
7 S6
8 S7
V+ 16
D 15
V – 14
DOUT 13
LTC1391
12
DIN
11
CS
10
CLK
9
GND
0.1µF OPTIONAL A/D
INPUT FILTER
1
VREF
8
VCC
2
+IN
7
CLK
3 LTC1285 6
–IN DOUT
45
GND CS/SHDN
1µF
SERIAL INTERFACE
TO MUX AND ADC
DATA IN
CLK
CS
DATA OUT
1391 TA01
On-Resistance vs
Analog Input Voltage
300
TA = 25°C
250
200
V+ = 2.7V
V – = 0V
150
100
V+ = 5V
50 V – = –5V
0
–5 –4 –3 –2 –1 0 1 2 3
ANALOG INPUT VOLTAGE (V)
45
1391 TA02
1
1 page  
LTC1391
APPLICATIONS INFORMATION
Multiplexer Operation
Figure 1 shows the block diagram of the components
within the LTC1391 required for MUX operation. The
LTC1391 uses DIN to select the active channel and the chip
select input, CS, to switch on the selected channel as
shown in Figure 2.
When CS is high, the input data on the DIN pin is latched
into the 4-bit shift register on the rising clock edge. The
input data consists of the “EN” bit and a string of three bits
for channel selection. If “EN” bit is logic high as illustrated
in the first input data sequence, it enables the selected
channel. After the clocking in of the last channel selection
bit B0, the CS pin must be pulled low before the next rising
clock edge to ensure correct operation. Once CS is pulled
low, the previously selected channel is switched off to
ensure a break-before-make interval. After a delay of tON,
the selected channel is switched on allowing signal trans-
mission. The selected channel remains on until the next
falling edge of CS. After a delay of tOFF, the LTC1391
terminates the analog signal transmission and allows the
CLK
DIN
CONTROL
LOGIC
CS
4-BIT SHIFT
REGISTER
ANALOG INPUTS
(S0 TO S7)
MUX
BLOCK
ANALOG
OUTPUT (D)
1391 • F01
Figure 1. Simplified Block Diagram of the MUX Operation
selection of next channel. If the “EN” bit is logic low, as
illustrated in the second data sequence, it disables all
channels and there will be no analog signal transmission.
Table 1 shows the various bit combinations for channel
selection.
Table 1. Logic Table for Channel Selection
ACTIVE CHANNEL
EN
B2
All Off
0X
S0 1 0
S1 1 0
S2 1 0
S3 1 0
S4 1 1
S5 1 1
S6 1 1
S7 1 1
B1
X
0
0
1
1
0
0
1
1
BO
X
0
1
0
1
0
1
0
1
Digital Data Transfer Operation
The block diagram of Figure 3 shows the components
within the LTC1391 required for serial data transfer. When
CS is held high, data is fed into the 4-bit shift register and
then shifted to DOUT. Data appears at DOUT after the fourth
rising edge of the clock as shown in Figure 4. The last four
CLK
DIN
CONTROL
LOGIC
CS
4-BIT SHIFT
REGISTER
DOUT
1391 F03
Figure 3. Simplified Block Diagram of the
Digital Data Transfer Operation
CLK
CS
DIN
ANY ANALOG
INPUT
D
EN B2 B1 B0
HIGH
EN LO B2 B1 B0
tON
Figure 2. Multiplexer Operation
tOFF
1391 • F02
5
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