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PDF SFC05-4 Data sheet ( Hoja de datos )
| Número de pieza | SFC05-4 | |
| Descripción | CSP TVS Flip Chip TVS Diode Array | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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PROTECTION PRODUCTS
Description
The SFC05-4 is a quad flip chip CSP TVS diode array.
They are state-of-the-art devices that utilize solid-state
silicon-avalanche technology for superior clamping
performance and DC electrical characteristics. The
SFC series TVS diodes are designed to protect sensi-
tive semiconductor components from damage or latch-
up due to electrostatic discharge (ESD) and other
voltage induced transient events.
The SFC05-4 is a 6-bump, 0.5mm pitch flip chip array
with a 3x2 bump grid. It measures 1.5 x 1.0 x
0.65mm. This small outline makes the SFC05-4
especially well suited for portable applications. CSP
TVS devices are compatible with current pick and place
equipment and assembly methods.
Each device will protect up to four data or I/O lines.
The CSP design results in lower inductance, virtually
eliminating voltage overshoot due to leads and inter-
connecting bond wires. They may be used to meet the
ESD immunity requirements of IEC 61000-4-2, Level 4
(15kV air, 8kV contact discharge).
SFC05-4
CSP TVS
Flip Chip TVS Diode Array
PRELIMINARY
Features
u 300 Watts peak pulse power (tp = 8/20µs)
u Transient protection for data lines to
IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 24A (8/20µs)
u Small chip scale package requires less board space
u Low profile (< 0.65mm)
u No need for underfill material
u Protects four I/O or data lines
u Low clamping voltage
u Working voltage: 5V
u Solid-state silicon-avalanche technology
Mechanical Characteristics
u JEDEC MO-211, Variation BB, 0.50 mm Pitch Chip
Scale Package (CSP)
u Marking : Marking Code
u Packaging : Tape and Reel
Applications
u Cell Phone Handsets and Accessories
u Personal Digital Assistants (PDAs)
u Notebook & Hand Held Computers
u Portable Instrumentation
u Pagers
u Smart Cards
u MP3 Players
u GPS
Device Dimensions
Schematic & PIN Configuration
1.50
1.00
0.50
B
0.50
TYP
0.65
0.150
SFC05-4 Maximum Dimensions (mm)
Revision 12/18/2000
1
A
1
23
3 x 2 Grid CSP TVS (Bottom View)
www.semtech.com
1 page  
PROTECTION PRODUCTS
Applications Information (Continued)
Printed Circuit Board Finish
A uniform board finish is critical for good assembly
yield. Two finishes that provide uniform surface coat-
ings are immersion nickel gold and organic surface
protectant (OSP). A non-uniform finish such as hot air
solder leveling (HASL) can lead to mounting problems
and should be avoided.
Stencil Design
A properly designed stencil is key to achieving ad-
equate solder volume without compromising assembly
yields. A 0.100mm thick, laser cut, electro-polished
stencil with 0.275mm square apertures and rounded
corners is recommended.
Reflow Profile
The flip chip TVS can be assembled using standard
SMT reflow processes. As with any component, ther-
mal profiles at specific board locations can vary & must
be determined by the manufacturer. The flip chip TVS
peak reflow temperature is 230 ± 10 °C, but the
device can withstand up to 260 °C peak reflow tem-
perature. Time above eutectic temperature (183 °C)
should be 50 ± 10 seconds. During reflow, the compo-
nent self-aligns itself on the pad.
Circuit Board Layout Recommendations for Suppres-
sion of ESD
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
l Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
l Minimize the path length between the TVS and the
protected line.
l Minimize all conductive loops including power and
ground loops.
l The ESD transient return path to ground should be
kept as short as possible.
l Never run critical signals near board edges.
l Use ground planes whenever possible.
ã 2000 Semtech Corp.
5
SFC05-4
PRELIMINARY
Stencil Design
Reflow Profile
www.semtech.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SFC05-4.PDF ] | |
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