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PDF OZ962R Data sheet ( 特性 )

部品番号 OZ962R
部品説明 High-Efficiency Inverter Controller
メーカ ETC
ロゴ ETC ロゴ 

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OZ962R Datasheet, OZ962R PDF,ピン配置, 機能
OZ962
High-Efficiency Inverter Controller
FEATURES
Single-stage power conversion, input voltage
range of 5V to 18V
Reduces the number of components and board
size by 30% compared with conventional design
Supports both floating and grounded secondary
designs
90% efficiency vs. typical 75% efficiency of
conventional designs
Internal open-lamp and short-circuit protections
Wide dimming range
Supports synchronization among multiple
inverter modules
Reliable 2 -winding transformer design,
eliminates arcing problems
Constant frequency, symmetrical, sinusoidal
drive
ORDERING INFORMATION
OZ962R - 16 lead TSSOP
OZ962G - 16-pin plastic SOP
GENERAL DESCRIPTION
The OZ962 is a unique high-efficiency, CCFL
backlight controller. It generates symmetrical,
near sinusoidal output voltage and current
waveforms for driving a CCFL backlight. The
OZ962 operates in a single, constant frequency,
pulse-width-modulation (PWM) mode. Typical
operating frequency ranges between 30 KHz to
100 KHz, depending on the CCFL and the
transformer’s characteristics.
Operating in a PWM push-pull manner, the
transformer in the OZ962 backlight inverter
requires only one primary winding and one
secondary winding, with the secondary winding
requiring no fold-back treatment.
The OZ962 is available in both 16-pin SOIC and
TSSOP packages. It is specified over the
commercial temperature range: 0 oC to +70 oC.
TYPICAL APPLICATION CIRCUIT
F1
VDD (+12V) 1A Fast Fuse
ENA
GND
CN1
R2
10K
R3
5.1K
+ C1
- 22u
25V
R1 R9
220K 200K C9
.01u
C2 C3
0.1u
330p
1
REF
U1
16
VDD
2 OZ962G 15
OVP
RT
3
NC
14
CT
4
SCP
13
CLK
5
ADJ
12
ENA
6
FB
11
NDR
7
CMP
10
PDR
8
GND
9
SST
R11 R4
1M 15K
R5
10K
C5
220p
C4
0.1u
R10
100
C8
0.22u
R7
100K
R6
30
3 U2
Q2 *
33T
4 C6 2.2u
5,6 50V
SI4559EY
-+
7,8
2
Q1
1
R8
0.5
R12
750
C7
* 68p
2200T 3KV
3.5W
R14
1.0K
R13
100
Figure 1. Typical Floating Secondary Application
Circuit
03/01/00
©Copyright 1999 by O2Micro
OZ962-SF -2.7
All Rights Reserved
Page 1
U.S. Patent #5,619,402

1 Page





OZ962R pdf, ピン配列
OZ962
PIN DESCRIPTION
Names
REF
OVP
NC
SCP
ADJ
FB
CMP
GND
SST
PDR
NDR
ENA
CLK
CT
RT
VDD
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
O
I
-
I
I
I
O
GND
I
O
O
I
O
I/O
I/O
PWR
Description
Reference voltage output. Nominal voltage is 2.5 V.
Over-voltage protection setting. Refer to formula for OVP in block diagram
on page 2 of this document.
No connection.
Short-circuit protection input.
Reference voltage input for dimming control.
Current sense feedback.
Compensation for the current sense feedback.
Ground.
Tsst ~ 0.2 Csst (Vdd - 5), where Csst is the soft start capacitor value in µF
and Tsst value is in µs.
Gate drive output for the P-MOSFET.
Gate drive output for the N-MOSFET.
Enable input, active high (Vth is about 1.7 V).
Open-drain clock output.
Timing capacitor. CT and RT set the clock frequency.
Timing resistor.
Supply voltage input.
ABSOLUTE MAXIMUM RATINGS
VDD
GND
Logic inputs
Power dissipation
18 V
+/- 0.3 V
-0.3 V to VDD+0.3 V
800 mW at 25 oC
Operating temp.
Operating junction temp.
Storage temp.
RECOMMENDED OPERATING RANGE
VDD
Fosc
Rosc
5V to 18V
30 KHz to 100 KHz
50 k to 150 k
0 oC to 70 oC
150 oC
-55 to 150 oC
OZ962-SF -2.7
Page 3


3Pages


OZ962R 電子部品, 半導体
OZ962
1
D
D
Be
EH
SOP-16
PACKAGE
Aα
A1
L
DIM
INCHES
MILLIMETERS
MIN MAX MIN MAX
A 0.0532 0.0688 1.35 1.75
A1 0.0040 0.0098 0.10 0.25
B 0.013 0.020 0.33 0.51
C 0.0075 0.0098 0.19 0.25
D 0.3859 0.3937 9.80 10.00
E 0.1497 0.1574 3.80 4.00
e 0.050 BCS.
1.27 BCS.
H 0.2284 0.244 5.80 6.20
0
L 0.016 0.050 0.40 1.27
α 0° 8° 0° 8°
C
OZ962-SF -2.7
Page 6

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