DataSheet.jp

1417G5A の電気的特性と機能

1417G5AのメーカーはAgere Systemsです、この部品の機能は「NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery」です。


製品の詳細 ( Datasheet PDF )

部品番号 1417G5A
部品説明 NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery
メーカ Agere Systems
ロゴ Agere Systems ロゴ 




このページの下部にプレビューと1417G5Aダウンロード(pdfファイル)リンクがあります。

Total 12 pages

No Preview Available !

1417G5A Datasheet, 1417G5A PDF,ピン配置, 機能
Data Sheet
January 2000
NetLight ® 1417G5 and 1417H5-Type
ATM/SONET/SDH Transceivers with Clock Recovery
Available in a small form factor, RJ-45 size, plastic package,
the 1417G5 and 1417H5-Type are high-performance, cost-
effective transceivers for ATM/SONET/SDH applications at
155 Mbits/s and 622 Mbits/s.
Features
s SONET/SDH Compliant (ITU-T G.957 Specifica-
tions)
— IR-1/S1.1, S4.1
s Small form factor, RJ-45 size, multisourced 20-pin
package
s Requires single 3.3 V power supply
s Clock recovery
s LC duplex receptacle
s Analog alarm outputs
s Uncooled 1300 nm laser transmitter with automatic
output power control
s Transmitter disable input
s Wide dynamic range receiver with InGaAs PIN
photodetector
s LVTTL signal-detect output
s Low power dissipation
s Raised ECL (PECL) logic data and clock interfaces
s Operating case temperature range: –40 °C to
+85 °C
s Agere Systems Inc. Reliability and Qualification
Program for built-in quality and reliability
Description
The 1417G5 and 1417H5 transceivers are high-
speed, cost-effective optical transceivers that are
compliant with the International Telecommunication
Union Telecommunication (ITU-T) G.957 specifica-
tions for use in ATM, SONET, and SDH applications.
The 1417G5 operates at the OC-3/STM-1 rate of
155 Mbits/s, and the 1417H5 operates at the OC-12/
STM-4 rate of 622 Mbits/s. The transceiver features
Agere Systems high-reliability optics and is pack-
aged in a narrow-width plastic housing with an LC
duplex receptacle. This receptacle fits into an RJ-45
form factor outline. The 20-pin package and pinout
conform to a multisource transceiver agreement.
The transmitter features differential PECL logic level
data inputs and a LVTTL logic level disable input. The
receiver features differential PECL logic level data
and clock outputs and a LVTTL logic level signal-
detect output.

1 Page





1417G5A pdf, ピン配列
Data Sheet
January 2000
NetLight 1417G5 and 1417H5-Type
ATM/SONET/SDH Transceivers with Clock Recovery
Pin Information (continued)
Table 1. Transceiver Pin Descriptions (continued)
Pin
Number
11
12
13
14
15
16
17
18
19
20
Symbol
VCCT
VEET
TDIS
TD+
TD–
VEET
BMON(–)
BMON(+)
PMON(–)
PMON(+)
Name/Description
Transmitter
Transmitter Power Supply.
Transmitter Signal Ground.
Transmitter Disable.
Transmitter Data In.
Transmitter Data In Bar.
Transmitter Signal Ground.
Laser Diode Bias Current Monitor—Negative End. The laser bias current
is accessible as a dc-voltage by measuring the voltage developed across pins
17 and 18.
Laser Diode Bias Current Monitor—Positive End. See pin 17 description.
Laser Diode Optical Power Monitor—Negative End. The back-facet diode
monitor current is accessible as a dc-voltage by measuring the voltage devel-
oped across pins 19 and 20.
Laser Diode Optical Power Monitor—Positive End. See pin 19 description.
Logic
Family
NA
NA
LVTTL
PECL
PECL
NA
NA
NA
NA
NA
Electrostatic Discharge
Caution: This device is susceptible to damage as
a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow EIA ® stan-
dard EIA-625.
Although protection circuitry is designed into the
device, take proper precautions to avoid exposure to
ESD. Agere Systems employs a human-body model
(HBM) for ESD-susceptibility testing and protection-
design evaluation. ESD voltage thresholds are depen-
dent on the critical parameters used to define the
model. A standard HBM (resistance = 1.5 k, capaci-
tance = 100 pF) is widely used and, therefore, can be
used for comparison purposes. The HBM ESD thresh-
old established for the 1417G5 and 1417H5 transceiv-
ers is ±1000 V.
Application Information
The 1417 receiver section is a highly sensitive fiber-
optic receiver. Although the data outputs are digital
logic levels (PECL), the device should be thought of as
an analog component. When laying out system appli-
cation boards, the 1417 transceiver should receive the
same type of consideration one would give to a sensi-
tive analog component.
Agere Systems Inc.
Printed-Wiring Board Layout Considerations
A fiber-optic receiver employs a very high-gain, wide-
bandwidth transimpedance amplifier. This amplifier
detects and amplifies signals that are only tens of nA in
amplitude when the receiver is operating near its sensi-
tivity limit. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver's sensitivity and can also degrade the perfor-
mance of the receiver's signal detect (SD) circuit. To
minimize the coupling of unwanted noise into the
receiver, careful attention must be given to the printed-
wiring board.
At a minimum, a double-sided printed-wiring board
(PWB) with a large component-side ground plane
beneath the transceiver must be used. In applications
that include many other high-speed devices, a multi-
layer PWB is highly recommended. This permits the
placement of power and ground on separate layers,
which allows them to be isolated from the signal lines.
Multilayer construction also permits the routing of sen-
sitive signal traces away from high-level, high-speed
signal lines. To minimize the possibility of coupling
noise into the receiver section, high-level, high-speed
signals such as transmitter inputs and clock lines
should be routed as far away as possible from the
receiver pins.
3


3Pages


1417G5A 電子部品, 半導体
NetLight 1417G5 and 1417H5-Type
ATM/SONET/SDH Transceivers with Clock Recovery
Data Sheet
January 2000
Qualification and Reliability
To help ensure high product reliability and customer satisfaction, Agere Systems is committed to an intensive qual-
ity program that starts in the design phase and proceeds through the manufacturing process. Optoelectronic mod-
ules are qualified to Agere Systems internal standards using MIL-STD-883 test methods and procedures and using
sampling techniques consistent with Telcordia Technologies requirements. The 1417 transceiver is required to pass
an extensive and rigorous set of qualification tests.
This qualification program fully meets the intent of Telcordia Technologies reliability practices TR-NWT-000468 and
TA-TSY-000983 requirements. In addition, the design, development, and manufacturing facilities of Agere Systems
Optoelectronics unit have been certified to be in full compliance with the latest ISO ® 9001 quality system stan-
dards.
Electrical Schematic
17 18 19 20
BMON–
BMON+
PMON–
PMON+
15
10
15
15
15
TRANSMITTER
DRIVER
SFF TRANSCEIVER
VPD
RECEIVER
POST-
AMPLIFIER/
CDR
200
VEET
12, 16
TD– 15
TD+
TDIS
14
13
VCCT 11
VCCR 7
RD+
RD–
CLK+
CLK–
SD
1
10
9
5
4
8
L2
C4 C5
L1
VCC
C2 C3
C1
L1 = L2 = 1 µH—4.7 µH*
C1 = C2 = 10 nF
C3 = 4.7 µF—10 µF
C4 = C5 = 4.7 µF—10 µF
VEER 2, 3, 6
* Ferrite beads can be used as an option.
† For all capacitors, MLC caps are recommended.
Figure 3. Power Supply Filtering for the Small Form Factor Transceiver
1-968(F).b
6 Agere Systems Inc.

6 Page



ページ 合計 : 12 ページ
 
PDF
ダウンロード
[ 1417G5A データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
1417G5

NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery

Agere Systems
Agere Systems
1417G5

NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery

Agere Systems
Agere Systems
1417G5A

NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery

Agere Systems
Agere Systems
1417G5A

NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery

Agere Systems
Agere Systems


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap