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HI5628 の電気的特性と機能

HI5628のメーカーはIntersilです、この部品の機能は「8-Bit / 165/125/60MSPS / Dual High Speed CMOS D/A Converter」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI5628
部品説明 8-Bit / 165/125/60MSPS / Dual High Speed CMOS D/A Converter
メーカ Intersil
ロゴ Intersil ロゴ 




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HI5628 Datasheet, HI5628 PDF,ピン配置, 機能
Data Sheet
HI5628
July 1999 File Number 4520.3
8-Bit, 165/125/60MSPS, Dual High Speed
CMOS D/A Converter
The HI5628 is an 8-bit, dual 125MSPS D/A converter which
is implemented in an advanced CMOS process. Operating
from a single +5V to +3V supply, the converter provides
20.48mA of full scale output current and includes an input
data register. Low glitch energy and excellent frequency
domain performance are achieved using a segmented
architecture. The single DAC version is the HI5660 while
10-bit versions exist in the HI5760 and HI5728. This DAC is
a member of the CommLink™ family of communication
devices.
Ordering Information
PART
NUMBER
TEMP.
RANGE
(oC)
MAX
CLOCK
PACKAGE PKG. NO. SPEED
HI5628/16IN-40 to 85 48 Ld LQFP Q48.7x7A 165MHz
HI5628IN
-40 to 85 48 Ld LQFP Q48.7x7A 125MHz
HI5628/6IN
-40 to 85 48 Ld LQFP Q48.7x7A 60MHz
HI5628EVAL1
25 Evaluation Platform
125MHz
Contact factory for availability.
Features
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 125MSPS
• Low Power . . . . . . . . . . . . . . 330mW at 5V, 170mW at 3V
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . ±0.25 LSB
• Differential Linearity . . . . . . . . . . . . . . . . . . . . . ±0.25 LSB
• Channel Isolation (Typ). . . . . . . . . . . . . . . . . . . . . . . 80dB
• SFDR to Nyquist at 10MHz Output . . . . . . . . . . . . 60dBc
• Internal 1.2V Bandgap Voltage Reference
• Single Power Supply from +5V to +3V
• CMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
Applications
• Direct Digital Frequency Synthesis
• Wireless Communications
• Signal Reconstruction
• Arbitrary Waveform Generators
• Test Equipment
• High Resolution Imaging Systems
Pinout
HI5628 (LQFP)
ID4
ID3
ID2
ID1
ID0 (LSB)
DGND
DGND
SLEEP
DVDD
DGND
NC
AVDD
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
1213 14
15 16
17 18 19
20
21 22
25
23 24
QD4
QD3
QD2
QD1
QD0 (LSB)
DGND
DGND
DVDD
DGND
NC
AVDD
AGND
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CommLink™ is a trademark of Intersil Corporation.

1 Page





HI5628 pdf, ピン配列
Functional Block Diagram
HI5628
IOUTA IOUTB
(LSB) ID0
ID1
ID2
ID3
ID4
ID5
ID6
(MSB) ID7
LATCH
UPPER
5-BIT
DECODER
31
34
LATCH
SWITCH
MATRIX
CASCODE
CURRENT
SOURCE
34
3 LSBs
+
31 MSB
SEGMENTS
ICLK
INT/EXT
REFERENCE
SELECT
INT/EXT
VOLTAGE
REFERENCE
BIAS
GENERATION
ICOMP1
REFLO
REFIO
FSADJ
SLEEP
(LSB) QD0
QD1
QD2
QD3
QD4
QD5
QD6
(MSB) QD7
QCLK
LATCH
QCOMP1
UPPER
5-BIT
DECODER
31
34
LATCH
SWITCH
MATRIX
CASCODE
CURRENT
SOURCE
34
3 LSBs
+
31 MSB
SEGMENTS
AVDD AGND DVDD DGND
QOUTA QOUTB
3


3Pages


HI5628 電子部品, 半導体
HI5628
Electrical Specifications AVDD = +5V, DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values. Data given
is per channel except for ‘Power Supply Characteristics.’ (Continued)
PARAMETER
TEST CONDITIONS
HI5628IN
TA = -40oC TO 85oC
MIN TYP MAX
UNITS
Reference Input Multiplying Bandwidth (Note 7)
DIGITAL INPUTS D7-D0, CLK (Per Channel)
Input Logic High Voltage with
(Note 3)
5V Supply, VIH
Input Logic High Voltage with
(Note 3)
3V Supply, VIH
Input Logic Low Voltage with
(Note 3)
5V Supply, VIL
Input Logic Low Voltage with
(Note 3)
3V Supply, VIL
Input Logic Current, IIH
Input Logic Current, IIL
Digital Input Capacitance, CIN
TIMING CHARACTERISTICS (Per Channel)
Data Setup Time, tSU
Data Hold Time, tHLD
Propagation Delay Time, tPD
CLK Pulse Width, tPW1, tPW2
POWER SUPPLY CHARACTERISTICS
See Figure 3 (Note 3)
See Figure 3 (Note 3)
See Figure 3
See Figure 3 (Note 3)
- 1.4 - MHz
3.5 5
-
V
2.1 3
-
V
-
0 1.3
V
-
0 0.9
V
-10 - +10 µA
-10 - +10 µA
- 5 - pF
3 - - ns
3 - - ns
- 1 - ns
4 - - ns
AVDD Power Supply
DVDD Power Supply
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)
(Note 8, 9)
(Note 8, 9)
5V or 3V, IOUTFS = 20mA
5V or 3V, IOUTFS = 2mA
5V, IOUTFS = Don’t Care (Note 5)
3V, IOUTFS = Don’t Care (Note 5)
2.7 5.0 5.5
2.7 5.0 5.5
- 46 60
-8-
- 6 10
-3-
V
V
mA
mA
mA
mA
Supply Current (IAVDD) Sleep Mode
Power Dissipation (Both Channels)
5V or 3V, IOUTFS = Don’t Care)
5V, IOUTFS = 20mA (Note 6)
- 3.2 6
- 330 -
mA
mW
5V, IOUTFS = 2mA (Notes 6)
- 140 -
mW
3V, IOUTFS = 20mA (Note 6)
- 170 -
mW
3V, IOUTFS = 2mA (Note 6)
- 54 - mW
5V, IOUTFS = 20mA (Note 10)
3.3V, IOUTFS = 20mA (Note 10)
3V, IOUTFS = 20mA (Note 10)
- 300 -
- 150 -
- 135 -
mW
mW
mW
Power Supply Rejection
Single Supply (Note 7)
-0.2 - +0.2 %
FSR/V
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no filtering.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz, both channels.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz, both channels.
7. See ‘Definition of Specifications’.
8. For operation below 3V, it is recommended that the output current be reduced to 12mA or less to maintain optimum performance. DVDD and
AVDD do not have to be equal.
9. For operation above 125MHz, it is recommended that the power supply be 3.3V or greater. The part is functional with the clock above 125MSPS
and the power supply below 3.3V, but performance is degraded. (Valid for 165MHz version only).
10. Measured with the clock at 60MSPS and the output frequency at 10MHz, both channels.
6

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部品番号部品説明メーカ
HI5628

8-Bit / 165/125/60MSPS / Dual High Speed CMOS D/A Converter

Intersil
Intersil


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