DataSheet.jp

93C56 の電気的特性と機能

93C56のメーカーはMicrochip Technologyです、この部品の機能は「2K 5.0V Automotive Temperature Microwire Serial EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 93C56
部品説明 2K 5.0V Automotive Temperature Microwire Serial EEPROM
メーカ Microchip Technology
ロゴ Microchip Technology ロゴ 




このページの下部にプレビューと93C56ダウンロード(pdfファイル)リンクがあります。

Total 12 pages

No Preview Available !

93C56 Datasheet, 93C56 PDF,ピン配置, 機能
M
93C56A/B
2K 5.0V Automotive Temperature Microwire® Serial EEPROM
FEATURES
• Single supply 5.0V operation
• Low power CMOS technology
- 1 mA active current (typical)
- 1 µA standby current (maximum)
• 256 x 8 bit organization (93C56A)
• 128 x 16 bit organization (93C56B)
• Self-timed ERASE and WRITE cycles (including
auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE
cycles
• Sequential READ function
• 100,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Available for the following temperature ranges:
- Automotive (E):
-40°C to +125°C
DESCRIPTION
The Microchip Technology Inc. 93C56A/B is a 2K-bit,
low-voltage serial Electrically Erasable PROM. The
device memory is configured as 256 x 8 bits (93C56A)
or 128 x 16 bits (93C56B). Advanced CMOS technol-
ogy makes this device ideal for low-power, nonvolatile
memory applications. The 93C56A/B is available in
standard 8-pin DIP and surface mount SOIC packages.
This device is only recommeded for 5V automotive
temperature applications. For all commercial and
industrial applications, the 93LC56A/B is recom-
mended.
PACKAGE TYPE
PDIP
CS
VCC
1
CLK 2
DI 3
DO 4
8
7 NC
6 NC
5 VSS
SOIC
CS
CLK
DI
DO
1
2
3
4
8 VCC
7 NC
6 NC
5 VSS
BLOCK DIAGRAM
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
COUNTER
DI
CS
CLK
DATA
REGISTER
MEMORY
DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
VCC
VSS
Microwire is a registered trademark of National Semiconductor.
© 1998 Microchip Technology Inc.
Preliminary
DS21206B-page 1

1 Page





93C56 pdf, ピン配列
93C56A/B
2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A high level selects the device. A low level deselects
the device and forces it into standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the CS input signal. If CS is
brought low during a program cycle, the device will go
into standby mode as soon as the programming cycle
is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93C56A/B.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
TABLE 2-1: INSTRUCTION SET FOR 93C56A
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detecting a START condition, the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
Note: CS must go low between consecutive
instructions.
2.3 Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4 Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation
has been initiated. The status signal is not available on
DO, if CS is held low during the entire ERASE or
WRITE cycle. In this case, DO is in the HIGH-Z mode.
If status is checked after the ERASE/WRITE cycle, the
data line will be high to indicate the device is ready.
.
Instruction SB Opcode
Address
Data In Data Out Req. CLK Cycles
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
1
1
1
1
1
1
1
11
X A7 A6 A5 A4 A3 A2 A1 A0
(RDY/BSY)
00 1 0 X X X X X X X —
(RDY/BSY)
00 0 0 X X X X X X X —
HIGH-Z
00 1 1 X X X X X X X —
HIGH-Z
10
X A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0
01 X A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)
00 0 1 X X X X X X X D7 - D0 (RDY/BSY)
12
12
12
12
20
20
20
TABLE 2-2: INSTRUCTION SET FOR 93C56B
Instruction SB Opcode
Address
Data In
ERASE 1
11
X A6 A5 A4 A3 A2 A1 A0
ERAL
1
00
1 0XXXXXX
EWDS 1 00 0 0 X X X X X X —
EWEN 1 00 1 1 X X X X X X —
READ 1
10
X A6 A5 A4 A3 A2 A1 A0
WRITE 1 01 X A6 A5 A4 A3 A2 A1 A0 D15 - D0
WRAL 1 00 0 1 X X X X X X D15 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D15 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
11
11
11
11
27
27
27
© 1998 Microchip Technology Inc.
Preliminary
DS21206B-page 4-3


3Pages


93C56 電子部品, 半導体
93C56A/B
3.6 ERASE/WRITE Disable and Enable
(EWDS/EWEN)
The device powers up in the ERASE/WRITE Disable
(EWDS) state. All programming modes must be pre-
ceded by an ERASE/WRITE Enable (EWEN) instruc-
tion. Once the EWEN instruction is executed,
programming remains enabled until an EWDS instruc-
tion is executed or VCC is removed from the device. To
protect against accidental data disturbance, the EWDS
instruction can be used to disable all ERASE/WRITE
functions and should follow all programming opera-
tions. Execution of a READ instruction is independent
of both the EWEN and EWDS instructions.
FIGURE 3-4: READ TIMING
CS
3.7 READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (93C56A) or 16-bit
(93C56B) output string. The output data bits will toggle
on the rising edge of the CLK and are stable after the
specified time delay (TPD). Sequential read is possible
when CS is held high. The memory data will automati-
cally cycle to the next register and output sequentially.
CLK
DI
DO
1 1 0 An ••• A0
HIGH-Z
0 Dx ••• D0 Dx ••• D0 Dx ••• D0
FIGURE 3-5: EWDS TIMING
CS
CLK
TCSL
DI
1 00
00
X
FIGURE 3-6: EWEN TIMING
CS
CLK
•••
X
TCSL
DI 1 0 0 1 1 X ••• X
DS21206B-page 6
Preliminary
© 1998 Microchip Technology Inc.

6 Page



ページ 合計 : 12 ページ
 
PDF
ダウンロード
[ 93C56 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
93C56

3-Wire Serial EEPROMs

ATMEL Corporation
ATMEL Corporation
93C56

16Kbit/ 8Kbit/ 4Kbit/ 2Kbit/ 1Kbit and 256bit 8-bit or 16-bit wide

STMicroelectronics
STMicroelectronics
93C56

Electrically Erasable Programmable Memories

National Semiconductor
National Semiconductor
93C56

2K 5.0V Automotive Temperature Microwire Serial EEPROM

Microchip Technology
Microchip Technology


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap