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8XC562 の電気的特性と機能

8XC562のメーカーはNXP Semiconductorsです、この部品の機能は「80C51 FAMILY DERIVATIVES」です。


製品の詳細 ( Datasheet PDF )

部品番号 8XC562
部品説明 80C51 FAMILY DERIVATIVES
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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8XC562 Datasheet, 8XC562 PDF,ピン配置, 機能
INTEGRATED CIRCUITS
80C51 FAMILY DERIVATIVES
8XC552/562 overview
1996 Aug 06
Philips
Semiconductors

1 Page





8XC562 pdf, ピン配列
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
(FFFFH) 64K
(FFFFH) 64K
EXTERNAL
(2000H) 8192
OVERLAPPED
SPACE
(1FFFH) 8191
INTERNAL
(EA = 1)
(0000H) 0
EXTERNAL
(EA = 0)
(FFH) 255
(7FH) 127
(00H) 0
INTERNAL
DATA RAM
SPECIAL
FUNCTION
REGISTERS
(0000H) 0
PROGRAM MEMORY
INTERNAL
DATA MEMORY
Figure 1. Memory Map
EXTERNAL
DATA MEMORY
SU00754
Timer T2
Timer T2 is a 16-bit timer consisting of two registers TMH2 (HIGH
byte) and TML2 (LOW byte). The 16-bit timer/counter can be
switched off or clocked via a prescaler from one of two sources:
fOSC/12 or an external signal. When Timer T2 is configured as a
counter, the prescaler is clocked by an external signal on T2 (P1.4).
A rising edge on T2 increments the prescaler, and the maximum
repetition rate is one count per machine cycle (1MHz with a 12MHz
oscillator).
The maximum repetition rate for Timer T2 is twice the maximum
repetition rate for Timer 0 and Timer 1. T2 (P1.4) is sampled at
S2P1 and again at S5P1 (i.e., twice per machine cycle). A rising
edge is detected when T2 is LOW during one sample and HIGH
during the next sample. To ensure that a rising edge is detected, the
input signal must be LOW for at least 1/2 cycle and then HIGH for at
least 1/2 cycle. If a rising edge is detected before the end of S2P1,
the timer will be incremented during the following cycle; otherwise it
will be incremented one cycle later. The prescaler has a
programmable division factor of 1, 2, 4, or 8 and is cleared if its
division factor or input source is changed, or if the timer/counter is
reset.
Timer T2 may be read “on the fly” but possesses no extra read
latches, and software precautions may have to be taken to avoid
misinterpretation in the event of an overflow from least to most
significant byte while Timer T2 is being read. Timer T2 is not
loadable and is reset by the RST signal or by a rising edge on the
input signal RT2, if enabled. RT2 is enabled by setting bit T2ER
(TM2CON.5).
When the least significant byte of the timer overflows or when a
16-bit overflow occurs, an interrupt request may be generated.
Either or both of these overflows can be programmed to request an
interrupt. In both cases, the interrupt vector will be the same. When
the lower byte (TML2) overflows, flag T2B0 (TM2CON) is set and
flag T20V (TM2IR) is set when TMH2 overflows. These flags are set
one cycle after an overflow occurs. Note that when T20V is set,
T2B0 will also be set. To enable the byte overflow interrupt, bits ET2
(IEN1.7, enable overflow interrupt, see Figure 2) and T2IS0
(TM2CON.6, byte overflow interrupt select) must be set. Bit TWB0
(TM2CON.4) is the Timer T2 byte overflow flag.
To enable the 16-bit overflow interrupt, bits ET2 (IE1.7, enable
overflow interrupt) and T2IS1 (TM2CON.7, 16-bit overflow interrupt
select) must be set. Bit T2OV (TM2IR.7) is the Timer T2 16-bit
overflow flag. All interrupt flags must be reset by software. To enable
both byte and 16-bit overflow, T2IS0 and T2IS1 must be set and two
interrupt service routines are required. A test on the overflow flags
indicates which routine must be executed. For each routine, only the
corresponding overflow flag must be cleared.
Timer T2 may be reset by a rising edge on RT2 (P1.5) if the Timer
T2 external reset enable bit (T2ER) in T2CON is set. This reset also
clears the prescaler. In the idle mode, the timer/counter and
prescaler are reset and halted. Timer T2 is controlled by the
TM2CON special function register (see Figure 3).
1996 Aug 06
3


3Pages


8XC562 電子部品, 半導体
Philips Semiconductors
80C51 Family Derivatives
8XC552/562 overview
TM2CON (EAH)
7
T2IS1
(MSB)
6
T2IS0
5
T2ER
4
T2BO
3
T2P1
2
T2P0
10
T2MS1 T2MS0
(LSB)
BIT
TM2CON.7
TM2CON.6
TM2CON.5
SYMBOL
TSIS1
T2IS0
T2ER
TM2CON.4
TM2CON.3
TM2CON.2
T2BO
T2P1
T2P0
FUNCTION
Timer T2 16-bit overflow interrupt select
Timer T2 byte overflow interrupt select
Timer T2 external reset enable. When this bit is set,
Timer T2 may be reset by a rising edge on RT2 (P1.5).
Timer T2 byte overflow interrupt flag
Timer T2 prescaler select
T2P1
0
0
1
1
T2P0
0
1
0
1
Timer T2 Clock
Clock source
Clock source/2
Clock source/4
Clock source/8
TM2CON.1
TM2CON.0
T2MS1
T2MS0
Timer T2 mode select
T2MS1 T2MS0
00
01
10
11
Mode Selected
Timer T2 halted (off)
T2 clock source = fOSC/12
Test mode; do not use
T2 clock source = pin T2
Figure 3. T2 Control Register (TM2CON)
SU00756
Timer T2 Extension: When a 12MHz oscillator is used, a 16-bit
overflow on Timer T2 occurs every 65.5, 131, 262, or 524 ms,
depending on the prescaler division ratio; i.e., the maximum cycle
time is approximately 0.5 seconds. In applications where cycle times
are greater than 0.5 seconds, it is necessary to extend Timer T2.
This is achieved by selecting fosc/12 as the clock source (set
T2MS0, reset T2MS1), setting the prescaler division ration to 1/8
(set T2P0, set T2P1), disabling the byte overflow interrupt (reset
T2IS0) and enabling the 16-bit overflow interrupt (set T2IS1). The
following software routine is written for a three-byte extension which
gives a maximum cycle time of approximately 2400 hours.
OVINT: PUSH
PUSH
INC
MOV
JNZ
ACC ;save accumulator
PSW ;save status
TIMEX1 ;increment first byte (low order)
;of extended timer
A,TIMEX1
INTEX ;jump to INTEX if ;there is no overflow
INC
MOV
JNZ
INC
TIMEX2 ;increment second byte
A,TIMEX2
INTEX ;jump to INTEX if there is no overflow
TIMEX3 ;increment third byte (high order)
INTEX: CLR
POP
POP
RETI
T2OV
PSW
ACC
;reset interrupt flag
;restore status
;restore accumulator
;return from interrupt
Timer T2, Capture and Compare Logic: Timer T2 is connected to
four 16-bit capture registers and three 16-bit compare registers. A
capture register may be used to capture the contents of Timer T2
when a transition occurs on its corresponding input pin. A compare
register may be used to set, reset, or toggle port 4 output pins at
certain pre-programmable time intervals.
The combination of Timer T2 and the capture and compare logic is
very powerful in applications involving rotating machinery,
automotive injection systems, etc. Timer T2 and the capture and
compare logic are shown in Figure 4.
Capture Logic: The four 16-bit capture registers that Timer T2 is
connected to are: CT0, CT1, CT2, and CT3. These registers are
loaded with the contents of Timer T2, and an interrupt is requested
upon receipt of the input signals CT0I, CT1I, CT2I, or CT3I. These
input signals are shared with port 1. The four interrupt flags are in
the Timer T2 interrupt register (TM2IR special function register). If
the capture facility is not required, these inputs can be regarded as
additional external interrupt inputs.
Using the capture control register CTCON (see Figure 5), these
inputs may capture on a rising edge, a falling edge, or on either a
rising or falling edge. The inputs are sampled during S1P1 of each
cycle. When a selected edge is detected, the contents of Timer T2
are captured at the end of the cycle.
1996 Aug 06
6

6 Page



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部品番号部品説明メーカ
8XC562

80C51 FAMILY DERIVATIVES

NXP Semiconductors
NXP Semiconductors


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