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8XC54 の電気的特性と機能

8XC54のメーカーはIntel Corporationです、この部品の機能は「CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER」です。


製品の詳細 ( Datasheet PDF )

部品番号 8XC54
部品説明 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 




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8XC54 Datasheet, 8XC54 PDF,ピン配置, 機能
8XC52 54 58
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Commercial Express
87C52 80C52 80C32 87C54 80C54 87C58 80C58
See Table 1 for Proliferation Options
Y High Performance CHMOS EPROM
ROM CPU
Y 12 24 33 MHz Operations
Y Three 16-Bit Timer Counters
Y Programmable Clock Out
Y Up Down Timer Counter
Y Three Level Program Lock System
Y 8K 16K 32K On-Chip Program Memory
Y 256 Bytes of On-Chip Data RAM
Y Improved Quick Pulse Programming
Algorithm
Y Boolean Processor
Y 32 Programmable I O Lines
Y 6 Interrupt Sources
Y Programmable Serial Channel with
Framing Error Detection
Automatic Address Recognition
Y TTL and CMOS Compatible Logic
Levels
Y 64K External Program Memory Space
Y 64K External Data Memory Space
Y MCS 51 Microcontroller Compatible
Instruction Set
Y Power Saving Idle and Power Down
Modes
Y ONCE (On-Circuit Emulation) Mode
Y Four-Level Interrupt Priority
Y Extended Temperature Range Except
for 33 MHz Offering (b40 C to a85 C)
MEMORY ORGANIZATION
ROM
Device
EPROM
Version
ROMless
Version
ROM EPROM
Bytes
80C52
80C54
80C58
87C52
87C54
87C58
80C32
80C32
80C32
8K
16K
32K
These devices can address up to 64 Kbytes of external program data memory
RAM
Bytes
256
256
256
The Intel 8XC52 8XC54 8XC58 is a single-chip control-oriented microcontroller which is fabricated on Intel’s
reliable CHMOS III-E technology Being a member of the MCS 51 family of controllers the 8XC52 8XC54
8XC58 uses the same powerful instruction set has the same architecture and is pin-for-pin compatible with
the existing MCS 51 family of products The 8XC52 8XC54 8XC58 is an enhanced version of the
87C51 80C51BH 80C31BH The added features make it an even more powerful microcontroller for applica-
tions that require clock output and up down counting capabilities such as motor control It also has a more
versatile serial channel that facilitates multi-processor communications
Throughout this document 8XC5X will refer to the 8XC52 80C32 8XC54 and 8XC58 unless information
applies to a specific device
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
March 1996
Order Number 272336-004

1 Page





8XC54 pdf, ピン配列
8XC52 54 58
PROCESS INFORMATION
This device is manufactured on P629 0 a CHMOS
III-E process Additional process and reliability infor-
mation is available in Intel’s Components Quality
and Reliability Handbook Order No 210997
PACKAGES
Part
Prefix
8XC5X
87C5X
8XC5X
8XC5X
P
D
N
S
Package Type
40-Pin Plastic DIP (OTP)
40-Pin CERDIP (EPROM)
44-Pin PLCC (OTP)
44-Pin QFP (OTP)
DIP
272336 –2
PLCC
272336 – 3
Do not connect reserved pins
QFP
Figure 2 Pin Connections
272336 – 4
3


3Pages


8XC54 電子部品, 半導体
8XC52 54 58
Mode
Idle
Idle
Power Down
Power Down
Table 2 Status of the External Pins during Idle and Power Down
Program
Memory
ALE
PSEN
PORT0
PORT1
PORT2
Internal
1
1
Data
Data
Data
External
1
1
Float
Data
Address
Internal
0
0
Data
Data
Data
External
0
0
Float
Data
Data
PORT3
Data
Data
Data
Data
POWER DOWN MODE
To save even more power a Power Down mode can
be invoked by software In this mode the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated
On the 8XC5X either a hardware reset or an external
interrupt can cause an exit from Power Down Reset
redefines all the SFRs but does not change the on-
chip RAM An external interrupt allows both the
SFRs and on-chip RAM to retain their values
To properly terminate Power Down the reset or ex-
ternal interrupt should not be executed before VCC is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms)
With an external interrupt INT0 and INT1 must be
enabled and configured as level-sensitive Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit Once the interrupt is
serviced the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down
DESIGN CONSIDERATION
 The window on the D87C5X must be covered by
an opaque label Otherwise the DC and AC char-
acteristics may not be met and the device may
be functionally impaired
 When the idle mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
is not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing and debugging of systems using the 8XC5X
without the 8XC5X having to be removed from the
circuit The ONCE Mode is invoked by
1) Pull ALE low while the device is in reset and
PSEN is high
2) Hold ALE low as RST is deactivated
While the device is in ONCE Mode the Port 0 pins
float and the other port pins and ALE and PSEN are
weakly pulled high The oscillator circuit remains ac-
tive While the 8XC5X is in this mode an emulator or
test CPU can be used to drive the circuit Normal
operation is restored when a normal reset is applied
NOTE
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I (Order No 270645) and Application Note AP-252 (Embedded Applications Handbook Order No
270648) ‘‘Designing with the 80C51BH ’’
6

6 Page



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共有リンク

Link :


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