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87C257 の電気的特性と機能

87C257のメーカーはSTMicroelectronicsです、この部品の機能は「ADDRESS LATCHED 256K 32K x 8 UV EPROM and OTP EPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 87C257
部品説明 ADDRESS LATCHED 256K 32K x 8 UV EPROM and OTP EPROM
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 




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87C257 Datasheet, 87C257 PDF,ピン配置, 機能
M87C257
ADDRESS LATCHED
256K (32K x 8) UV EPROM and OTP EPROM
INTEGRATED ADDRESS LATCH
FAST ACCESS TIME: 45ns
LOW POWER “CMOS” CONSUMPTION:
– Active Current 30mA
– Standby Current 100µA
PROGRAMMING VOLTAGE: 12.75V
ELECTRONIC SIGNATURE for AUTOMATED
PROGRAMMING
PROGRAMMING TIMES of AROUND 3sec.
(PRESTO II ALGORITHM)
28
1
FDIP28W (F)
PLCC32 (C)
DESCRIPTION
The M87C257 is a high speed 262,144 bit UV
erasable and electrically programmable EPROM.
The M87C257 incorporates latches for all address
inputs to minimize chip count, reduce cost, and
simplify the design of multiplexed bus systems.
The Window Ceramic Frit-Seal Dual-in-Line pack-
age has a transparent lid which allows the user to
expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M87C257 is offered in Plastic Leaded Chip Carrier,
package.
Table 1. Signal Names
A0 - A14
Address Inputs
Q0 - Q7
Data Outputs
E Chip Enable
G Output Enable
ASVPP
VCC
VSS
Address Strobe / Program Supply
Supply Voltage
Ground
Figure 1. Logic Diagram
VCC
15
A0-A14
E
G
ASVPP
M87C257
VSS
8
Q0-Q7
AI00928B
June 1996
1/13

1 Page





87C257 pdf, ピン配列
M87C257
Table 3. Operating Modes
Mode
E
Read (Latched Address)
VIL
Read (Applied Address)
VIL
Output Disable
VIL
Program
VIL Pulse
Verify
VIH
Program Inhibit
VIH
Standby
VIH
Electronic Signature
Note: X = VIH or VIL, VID = 12V ± 0.5V
VIL
G
VIL
VIL
VIH
VIH
VIL
VIH
X
VIL
A9
ASVPP
Q0 - Q7
X VIL Data Out
X VIH Data Out
X X Hi-Z
X VPP Data In
X VPP Data Out
X VPP Hi-Z
X X Hi-Z
VID VIL Codes
Table 4. Electronic Signature
Identifier
A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data
Manufacturer’s Code VIL
0
0
1
0
0
0
0
0
Device Code
VIH 1 0 0 0 0 0 0 0
20h
80h
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable (AS = VIH) or latched (AS =
VIL), the address access time (tAVQV) is equal to the
delay from E to output (tELQV). Data is available at
the output after delay of tGLQV from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least tAVQV-tGLQV.
The M87C257 reduces the hardware interface in
multiplexed address-data bus systems. The proc-
essor multiplexed bus (AD0-AD7) may be tied to
the M87C257’s address and data pins. No sepa-
rate address latch is needed because the
M87C257 latches all address inputs when AS is
low.
Standby Mode
The M87C257 has a standby mode which reduces
the active current from 30mA to 100µA (Address
Stable). The M87C257 is placed in the standby
mode by applying a CMOS high signal to the E
input. When in the standby mode, the outputs are
in a high impedance state, independent of the G
input.
Two Line Output Control
Because EPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is desired from a particular memory device.
3/13


3Pages


87C257 電子部品, 半導体
M87C257
Table 8B. Read Mode AC Characteristics (1)
(TA = 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Alt
Parameter
tAVQV
tAVASL
tACC
Address Valid to
Output Valid
tAL
Address Valid to
Address Strobe Low
Test
Condition
E = VIL, G = VIL
M87C257
-90 -10 -12 -15/-20 Unit
Min Max Min Max Min Max Min Max
90 100 120 150 ns
7 7 7 7 ns
tASHASL
tLL
Address Strobe High
to Address Strobe Low
35 35 35 35 ns
tASLAX
tASLGL
tELQV
tLA
Address Strobe Low to
Address Transition
tLOE
Address Strobe Low
to Output Enable Low
tCE
Chip Enable Low to
Output Valid
G = VIL
20 20 20 20 ns
20 20 20 20 ns
90 100 120 150 ns
tGLQV
tEHQZ (2)
tGHQZ (2)
tOE
Output Enable Low to
Output Valid
tDF
Chip Enable High to
Output Hi-Z
tDF
Output Enable High to
Output Hi-Z
E = VIL
G = VIL
E = VIL
40 40 50 60 ns
0 40 0 30 0 40 0 40 ns
0 40 0 30 0 40 0 40 ns
tAXQX
tOH
Address Transition to
Output Transition
E = VIL, G = VIL
0
0
0
Notes: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
0 ns
Figure 5. Read Mode AC Waveforms
A0-A14
ASVPP
E
G
Q0-Q7
VALID
tAVASL
tASLAX
tASHASL
tASLGL
tAVQV
tGLQV
tELQV
tAXQX
tEHQZ
tGHQZ
DATA OUT
Hi-Z
AI00931
6/13

6 Page



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