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7490 PDF Data sheet ( 特性 )

部品番号 7490
部品説明 Decade and Binary Counters
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 



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7490 Datasheet, 7490 PDF,ピン配置, 機能
August 1986
Revised March 2000
DM7490A
Decade and Binary Counters
General Description
The DM7490A monolithic counter contains four master-
slave flip-flops and additional gating to provide a divide-by-
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five.
The counter has a gated zero reset and also has gated set-
to-nine inputs for use in BCD nine’s complement applica-
tions.
To use the maximum count length (decade or four-bit
binary), the B input is connected to the QA output. The
input count pulses are applied to input A and the outputs
are as described in the appropriate Function Table. A sym-
metrical divide-by-ten count can be obtained from the
counters by connecting the QD output to the A input and
applying the input count to the B input which gives a divide-
by-ten square wave at output QA.
Features
s Typical power dissipation
145 mW
s Count frequency 42 MHz
Ordering Code:
Order Number Package Number
Package Description
DM7490AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
© 2000 Fairchild Semiconductor Corporation DS006533
www.fairchildsemi.com

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