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83C652 の電気的特性と機能

83C652のメーカーはNXP Semiconductorsです、この部品の機能は「CMOS single-chip 8-bit microcontrollers」です。


製品の詳細 ( Datasheet PDF )

部品番号 83C652
部品説明 CMOS single-chip 8-bit microcontrollers
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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83C652 Datasheet, 83C652 PDF,ピン配置, 機能
INTEGRATED CIRCUITS
80C652/83C652
CMOS single-chip 8-bit microcontrollers
Product specification
Supersedes data of 1996 Aug 15
IC20 Data Handbook
1997 Dec 05
Philips
Semiconductors

1 Page





83C652 pdf, ピン配列
Phlips Semiconductors
CMOS single-chip 8-bit microcontrollers
PLASTIC LEADED CHIP CARRIER
PIN FUNCTIONS
6 1 40
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44 34
7 39
PLASTIC
LEADED CHIP
CARRIER
17 29
1 33
PLASTIC
QUAD
FLAT
PACK
11 23
18
Pin Function
1 NC*
2 P1.0
3 P1.1
4 P1.2
5 P1.3
6 P1.4
7 P1.5
8 P1.6/SCL
9 P1.7/SDA
10 RST
11 P3.0/RxD
12 NC*
13 P3.1/TxD
14 P3.2/INT0
15 P3.3/INT1
16 P3.4/T0
17 P3.5/T1
18 P3.6/WR
19 P3.7/RD
20 XTAL2
21 XTAL1
22 VSS
*DO NOT CONNECT
28
Pin Function
23 NC*
24 P2.0/A8
25 P2.1/A9
26 P2.2/A10
27 P2.3/A11
28 P2.4/A12
29 P2.5/A13
30 P2.6/A14
31 P2.7/A15
32 PSEN
33 ALE
34 NC*
35 EA
36 P0.7/AD7
37 P0.6/AD6
38 P0.5/AD5
39 P0.4/AD4
40 P0.3/AD3
41 P0.2/AD2
42 P0.1/AD1
43 P0.0/AD0
44 VDD
12
Pin Function
1 P1.5
2 P1.6/SCL
3 P1.7/SDA
4 RST
5 P3.0/RxD
6 VSS4
7 P3.1/TxD
8 P3.2/INT0
9 P3.3/INT1
10 P3.4/T0
11 P3.5/T1
12 P3.6/WR
13 P3.7/RD
14 XTAL2
15 XTAL1
16 VSS1
17 NC*
18 P2.0/A8
19 P2.1/A9
20 P2.2/A10
21 P2.3/A11
22 P2.4/A12
22
Pin Function
23 P2.5/A13
24 P2.6/A14
25 P2.7/A15
26 PSEN
27 ALE
28 VSS2
29 EA/VPP
30 P0.7/AD7
31 P0.6/AD6
32 P0.5/AD5
33 P0.4/AD4
34 P0.3/AD3
35 P0.2/AD2
36 P0.1/AD1
37 P0.0/AD0
38 VDD
39 VSS3
40 P1.0
41 P1.1
42 P1.2
43 P1.3
44 P1.4
*DO NOT CONNECT
NOTES TO QFP ONLY:
1. Due to EMC improvements, all VSS pins
(6, 16, 28, 39) must be connected to VSS
on the 80C652/83C652.
Product specification
80C652/83C652
1997 Dec 05
3


3Pages


83C652 電子部品, 半導体
Phlips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C652/83C652
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP PLCC QFP TYPE NAME AND FUNCTION
VSS 20 22 6, 16, I Ground: 0V reference. With the QFP package all VSS pins (VSS1 to VSS4) must be
28, 39
connected.
VDD
40 44
38
I Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0–0.7
39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
P1.6
P1.7
1–8 2–9 40–44, I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
1–3 which are open drain. Port 1 pins that have 1s written to them are pulled high by the
internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled
low will source current because of the internal pull-ups. (See DC Electrical Characteristics:
78
IIL). Alternate functions include:
2 I/O
SCL: I2C-bus serial port clock line.
89
3 I/O
SDA: I2C-bus serial port data line.
P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0–P3.7 10–17 11,
5,
13–19 7–13
10 11
11 13
12 14
13 15
14 16
15 17
16 18
17 19
5
7
8
9
10
11
12
13
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of
the 80C51 family, as listed below:
I RxD (P3.0): Serial input port
O TxD (P3.1): Serial output port
I INT0 (P3.2): External interrupt
I INT1 (P3.3): External interrupt
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
RST
ALE
9 10
4
I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VDD.
30 33 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency. Note that one ALE pulse is skipped during each access to external
data memory.
PSEN
29 32
26
O Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It
is activated twice each machine cycle during fetches from the external program memory.
When executing out of external program memory two activations of PSEN are skipped
during each access to external data memory. PSEN is not activated (remains HIGH) during
no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs and can
drive CMOS inputs without external pull–ups.
EA
31 35
29
I External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out
of the internal program memory ROM provided the Program Counter is less than 8192. If
during a RESET, EA is held a TTL LOW level, the CPU executes out of external program
memory. EA is not allowed to float.
XTAL1
19 21
15
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
18 20
14
O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VDD + 0.5V or VSS – 0.5V, respectively.
1997 Dec 05
6

6 Page



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部品番号部品説明メーカ
83C652

CMOS single-chip 8-bit microcontrollers

NXP Semiconductors
NXP Semiconductors
83C652

CMOS single-chip 8-bit microcontrollers

NXP Semiconductors
NXP Semiconductors
83C654

CMOS single-chip 8-bit microcontroller

NXP Semiconductors
NXP Semiconductors


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